IP Library › Granted Patent US 12,660,678
Granted Patent B2
US 12,660,678 · App. 17/479,302 · Granted Jun 16, 2026

Embedded package with delamination mitigation

Inventors: Bernd Schmoelzer (Radenthein, AT); Edward Fuergut (Dasing, DE); Ivan Nikitin (Regensburg, DE); Wolfgang Scholz (Olching, DE)
Assignee: Infineon Technologies Austria AG
H10W74/147H10W20/20H10W74/017H10W74/127H10W74/134H10W74/47H05K1/186
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Quick Facts
Patent No.
US 12,660,678
App. No.
17/479,302
Granted
Jun 16, 2026
Kind
B2
Abstract

A semiconductor assembly includes a laminate substrate that includes a plurality of laminate layers of electrically insulating material stacked on top of one another, a semiconductor package that includes a package body of electrically insulating encapsulant material and a plurality of electrical contacts that are exposed from the package body, wherein the semiconductor package is embedded within the laminate layers of the laminate substrate, wherein the semiconductor package comprises a delamination mitigation feature, wherein the delamination mitigation feature comprises one or both of a macrostructure that engages with the laminate layers, and a roughened surface of microstructures that enhances adhesion between the semiconductor package and the laminate layers.

Claims (16)

1 . A method of forming a semiconductor assembly, the method comprising:

providing a semiconductor package that comprises a package body of electrically insulating encapsulant material and a plurality of electrical contacts that are exposed from the package body;

forming a delamination mitigation feature in the semiconductor package; and

embedding the semiconductor package in a laminate substrate that comprises a plurality of laminate layers of electrically insulating material stacked on top of one another,

wherein the delamination mitigation feature prevents delamination between a surface of the semiconductor package and the laminate layers,

wherein the delamination mitigation feature comprises one or both of:

a macrostructure that engages with the laminate layers; and

a roughened surface of microstructures that enhances adhesion between the semiconductor package and the laminate layers,

wherein providing the semiconductor package comprises forming the package body by a molding process, and wherein the delamination mitigation feature is formed during the molding process,

wherein forming the delamination mitigation feature comprises adapting a molding cavity of the molding process to produce the package body to have the roughened surface of microstructures.

2 . The method of claim 1 , wherein forming the delamination mitigation feature comprises using pins to displace liquified encapsulant material during the molding process, and wherein depressions formed by the pins form the macrostructure that engages with the laminate layers.

3 . The method of claim 1 , wherein the delamination mitigation feature is formed in the semiconductor package after providing the semiconductor package.

4 . The method of claim 3 , wherein forming the delamination mitigation feature comprises performing one or more process steps that increase the surface area of an outer surface of the semiconductor package.

5 . The method of claim 4 , wherein the one or more process steps comprise removing portions of the encapsulant material so as to form a channel in the package body, and wherein the channel forms the macrostructure that engages with the laminate layer.

6 . The method of claim 4 , wherein forming the delamination mitigation feature comprises performing a surface treatment to the semiconductor package that creates the roughened surface of microstructures in the package body.

7 . The method of claim 6 , wherein the semiconductor package comprises a mold tool release agent on the package body, and wherein forming the delamination mitigation feature comprises removing the mold tool release agent from the package body.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 30, 2021
From: SCHMOELZER, BERND; FUERGUT, EDWARD; NIKITIN, IVAN; SCHOLZ, WOLFGANG
To: INFINEON TECHNOLOGIES AUSTRIA AG
Reel/Frame 057655/0359 →
Continuity (1)
Related Publication 20230106642A1 · Apr 6, 2023
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