IP Library › Granted Patent US 7,306,974
Granted Patent B2
US 7,306,974 · App. 11/206,012 · Granted Dec 11, 2007

Microelectronic devices and methods for manufacturing and operating packaged microelectronic device assemblies

Assignee: Micron Technology, Inc.
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Quick Facts
Patent No.
US 7,306,974
App. No.
11/206,012
Granted
Dec 11, 2007
Kind
B2
Abstract

Packaged microelectronic devices, methods for packaging microelectronic devices, and methods of operating microelectronic devices. In one embodiment, a packaged microelectronic device comprises a die including integrated circuitry, a first casing coating at least a portion of the die, a heat sink proximate to the die, and a second casing on at least a portion of the heat sink and coating at least a portion of the first casing. The first casing has a plurality of first interconnect elements, and the second casing engages the first interconnect elements to the first casing. The interconnect elements can be surface striations or other features that project into or away from the first casing. For example, the interconnect elements can be ridges extending across a surface of the first casing. In other embodiments, the first interconnect elements can be bumps and/or dimples across the surface of the first casing. The second casing can be molded around the first casing such that the material of the second casing conforms to or otherwise engages the first interconnect elements.

Claims (32)

1. A method of manufacturing a microelectronic device having a die including an integrated circuit, comprising:

injection molding a first casing to have an outer surface and a plurality of first elongated interconnecting elements extending across the outer surface and projecting into and/or away from the outer surface, wherein the first casing covers at least a portion of the die; and

covering a portion of the first casing with a second casing that has second elongated interconnecting elements engaged with the first elongated interconnecting elements of the first casing.

2. The method of claim 1 wherein:

forming the first casing comprises molding a first cover to have an outer surface and a plurality of elongated ridges extending across the outer surface that define the first elongated interconnecting elements; and

covering the first casing with the second casing comprises molding a second cover around at least a portion of the first cover, wherein the second cover has channels that defined the second elongated interconnecting elements.

3. The method of claim 1 wherein:

forming the first casing comprises molding a first cover to have an outer surface and a plurality of channels across the outer surface that define the first elongated interconnecting elements; and

covering the first casing with the second casing comprises molding a second cover around at least a portion of the first cover, wherein the second cover has elongated ridges that define the second elongated interconnecting elements.

4. The method of claim 1 wherein:

forming the first casing comprises molding a first cover to have an outer surface and a plurality of lands across the outer, the lands being separated by first channels extending in a first direction and second channels extending in a second direction transverse to the first direction, and wherein the first and second channels define the first elongated interconnecting elements; and

covering the first casing with the second casing comprises molding a second cover around at least a portion of the first cover, wherein the second cover conforms to the lands and has ridges in the first and second channels that define the second elongated interconnecting elements.

5. A method of manufacturing a microelectronic device, comprising:

providing a die having an integrated circuit;

encasing at least a portion of the die with an injection molding compound forming a first casing having an elongated coupling element extending across an outer surface of the casing and projecting into and/or away from the outer surface;

positioning a heat sink proximate to the die; and

covering at least a portion of the first casing and the heat sink with a second casing having an elongated mating element engaging the elongated coupling element.

6. The method of claim 5 wherein:

encasing at least a portion of the die with the first casing comprises molding a first cover to have an outer surface and a plurality of elongated ridges extending across the outer surface that define elongated coupling elements; and

covering the first casing with the second casing comprises molding a second cover around at least a portion of the first cover, wherein the second cover has channels defining elongated mating elements that receive the elongated ridges.

7. The method of claim 5 wherein:

encasing at least a portion of the die with the first casing comprises molding a first cover to have an outer surface and a plurality of channels across the outer surface that define elongated coupling elements; and

covering the first casing with the second casing comprises molding a second cover around at least a portion of the first cover, wherein the second cover has elongated mating elements defined by elongated ridges received in the channels of the first casings.

8. The method of claim 5 wherein:

encasing at least a portion of the die with the first casing comprises molding a first cover to have an outer surface and a plurality of lands across the outer surface, the lands being separated by first channels extending a first direction and second channels extending in a second direction transverse to the first direction, wherein the first and second channels define elongated coupling elements; and

covering the first casing with the second casing comprises molding a second cover around at least a portion of the first cover, wherein the second cover conforms to the lands and has ridges in the first and second channels that define the elongated mating elements.

9. A method of manufacturing a microelectronic device, comprising:

providing a die having integrated circuitry forming a memory device and a plurality of bond-pads coupled to the integrated circuitry;

attaching the die to a distribution member having a plurality of electrical connectors, the bond-pads being electrically coupled to corresponding electrical connectors;

molding a first casing to enclose at least a portion of the die and the distribution member, wherein molding the first casing further includes forming a coupling member on the first casing;

positioning a heat dissipation unit proximate to at least one of the die, the distribution member, and/or the first casing; and

molding a second casing to enclose at least a portion of the first casing and the heat dissipation unit, wherein the second casing engages the coupling member.

Assignments (7)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
Continuity (2)
Division 1021550900 · Aug 8, 2002
Related Publication 20060040422A1 · Feb 23, 2006