Systems and methods for improved adhesion between a leadframe and molding compound in a semiconductor device
An integrated circuit device having improved delamination properties is provided. The integrated circuit may include a leadframe having a die support area supporting an integrated circuit die, and a plurality of leadframe leads. Surfaces of the leadframe leads are roughened by a roughening process to form roughened surfaces having an average roughness R a . A thin plating layer is formed over the roughened leadframe lead surfaces, with a plating layer thickness of less than 40 times the roughness R a of the leadframe lead surfaces, such that the thin plating layer is received into the roughened leadframe lead surface contours and thereby itself has a contoured outer surface. A molding material applied to the structure may directly contact and adhere to the contoured surface of the thin plating layer. The adhesion between the molding material and the contoured plating layer may reduce or eliminate delamination of the molding material from the leadframe.
1. A method for manufacturing an integrated circuit device, the method comprising:
providing a leadframe comprising:
a die support area configured to receive an integrated circuit die; and
a leadframe lead adjacent the die support area;
after providing the leadframe, roughening a surface of the leadframe lead to form a roughened leadframe lead surface having three-dimensional contours having an average roughness Ra defined by an average distance from the roughened leadframe lead surface to a mean plane of the roughened leadframe lead surface, along a direction perpendicular to the mean plane;
forming a thin plating layer over at least a portion of the roughened leadframe lead surface to define a plated leadframe lead area, the thin plating layer having a thickness of less than 40 times the average roughness Ra of the roughened leadframe lead surface, such that the thin plating layer is received into the three-dimensional contours of the roughened leadframe lead surface and thereby forms a three-dimensionally contoured surface at an outer surface of the thin plating layer; and
applying a molding material over the leadframe and integrated circuit die such that the molding material contacts and adheres to the three-dimensionally contoured surface at the outer surface of the thin plating layer.
2. The method of claim 1 , wherein the thin plating layer comprises silver.
3. The method of claim 1 , wherein the leadframe comprises copper, and the thin plating layer comprises silver.
4. The method of claim 1 , wherein:
the leadframe comprises a plurality of leadframe leads adjacent the die support area; and
the method comprises roughening a surface of each leadframe lead to form a roughened leadframe lead surface on each leadframe lead, and forming a thin plating layer on each roughened leadframe lead surface, wherein a ratio of the thin plating layer thickness to the average roughness Ra of the respective roughened leadframe lead surface is less than 40.
5. The method of claim 1 , further comprising forming a wire bond between the plated leadframe lead area of the leadframe lead and the integrated circuit die on the die support area; and
wherein the molding material is applied over the wire bond.
6. The method of claim 1 , wherein:
the leadframe lead includes a first area and a second area adjacent the first area;
roughening a surface of the leadframe lead comprises roughening a surface of both the first area and the second area of the leadframe lead to form a roughened first area surface and a roughened second area surface; and
forming a thin plating layer over the roughened leadframe lead surface comprises forming a thin plating layer over the roughened first area surface but not over the roughened second area surface.
7. The method of claim 6 , wherein:
the first area of the leadframe lead, on which the thin plating layer is formed, is located at an end of the leadframe lead adjacent the die support area; and
the second area of the leadframe lead, on which the thin plating layer is not formed, is located away from the end of the leadframe lead, such that the first area of the leadframe lead is located between the second area of the leadframe lead and the die support area.
8. The method of claim 6 , wherein:
the second area of the leadframe lead, on which the thin plating layer is not formed, is located at an end of the leadframe lead adjacent the die support area; and
the first area of the leadframe lead, on which the thin plating layer is formed, is located away from the end of the leadframe lead, such that the second area of the leadframe lead is located between the first area of the leadframe lead and the die support area.
9. The method of claim 6 , comprising applying the molding material over both the first area and second area of the leadframe lead, such that the molding material (a) directly contacts the thin plating layer formed on the first area of the leadframe lead and (b) directly contacts the roughened second area surface of the second area of the leadframe lead, which is free of the thin plating layer.
10. The method of claim 1 , wherein the thickness of the thin plating layer is less than or equal to 3.75 μm.
11. The method of claim 1 , wherein:
the average roughness Ra of the roughened leadframe lead surface is at least 0.150 μm; and
the thickness of the thin plating layer is less than or equal to 3.75 μm.
12. The method of claim 4 , wherein the ratio of the thin plating layer thickness to the average roughness Ra of the respective roughened leadframe lead surface is less than 30.
13. The method of claim 4 , wherein the ratio of the thin plating layer thickness to the average roughness Ra of the respective roughened leadframe lead surface is less than 20.
14. The method of claim 4 , wherein the ratio of the thin plating layer thickness to the average roughness Ra of the respective roughened leadframe lead surface is less than 10.
15. The method of claim 4 , wherein the ratio of the thin plating layer thickness to the average roughness Ra of the respective roughened leadframe lead surface is less than 5.
16. The method of claim 1 , further comprising:
roughening a surface of the die support area; and
securing the integrated circuit die to the roughened surface of the die support area using an epoxy.
17. The method of claim 1 , further comprising:
forming the leadframe by a process including forming a wafer and cutting the wafer into a plurality of leadframes; and
wherein roughening the surface of the leadframe lead is performed after forming the leadframe.
18. An integrated circuit structure, comprising:
a leadframe comprising:
a die support area configured to receive an integrated circuit die; and
a plurality of leadframe leads adjacent the die support area, each leadframe lead including a finger tip area at one end of the leadframe lead;
wherein at least one of the leadframe leads has a roughening leadframe lead surface formed by a roughening process, each roughening leadframe lead surface having three-dimensional contours having an average roughness Ra defined by an average distance from the respective roughened leadframe lead surface to a mean plane of the respective roughened leadframe lead surface, along a direction perpendicular to the mean plane;
a thin plating layer formed over at least a portion of each roughened leadframe lead surface, the thin plating layer on each roughened leadframe lead surface having a thickness of less than 40 times the average roughness Ra of the respective roughened leadframe lead surface, such that each respective thin plating layer is received into the three-dimensional contours of the respective roughened leadframe lead surface and thereby forms a three-dimensionally contoured surface at an outer surface of the respective thin plating layer; and
a molding material formed over the leadframe and integrated circuit die such that the molding material contacts and adheres to the three-dimensionally contoured surface at the outer surface of each thin plating layer.
19. The integrated circuit structure of claim 18 , wherein:
each leadframe lead includes a first area having a roughened first area surface and a second area adjacent the first area and having a roughened second area surface; and
the thin plating layer is formed over the roughened first area surface but not over the roughened second area surface of each respective leadframe lead.
20. The integrated circuit structure of claim 19 , wherein the molding material is formed over both the first area and second area of each leadframe lead, such that the molding material (a) directly contacts the thin plating layer formed on the first area of each respective leadframe lead and (b) directly contacts the roughened second area surface of the second area of each respective leadframe lead.
21. The integrated circuit structure of claim 18 , wherein:
the average roughness Ra of each roughened leadframe lead surface is at least 0.150 μm; and
the thickness of the thin plating layer formed over each roughened leadframe lead surface is less than or equal to 3.75 μm.
22. The integrated circuit structure of claim 18 , wherein the thickness of the of the thin plating layer on each roughened leadframe lead surface is less than 10 times the average roughness R a of the respective roughened leadframe lead surface.
23. The integrated circuit structure of claim 19 , wherein:
the second area of the leadframe lead, on which the thin plating layer is not formed, is located at an end of the leadframe lead adjacent the die support area; and
the first area of the leadframe lead, on which the thin plating layer is formed, is located away from the end of the leadframe lead, such that the second area of the leadframe lead is located between the first area of the leadframe lead and the die support area.
24. An integrated circuit device including a leadframe having a die support area with an integrated circuit die mounted thereon and a leadframe lead adjacent the die support area, the integrated circuit device produced by a method comprising:
roughening a surface of the leadframe lead to form a roughened leadframe lead surface having three-dimensional contours having an average roughness Ra defined by an average distance from the roughened leadframe lead surface to a mean plane of the roughened leadframe lead surface, along a direction perpendicular to the mean plane;
forming a thin plating layer over at least a portion of the roughened leadframe lead surface to define a plated leadframe lead area, the thin plating layer having a thickness of less than 40 times the average roughness Ra of the roughened leadframe lead surface, such that the thin plating layer is received into the three-dimensional contours of the roughened leadframe lead surface and thereby forms a three-dimensionally contoured surface at an outer surface of the thin plating layer; and
applying a molding material over the leadframe and integrated circuit die such that the molding material contacts and adheres to the three-dimensionally contoured surface at the outer surface of the thin plating layer.
25. An integrated circuit device of claim 24 , wherein:
the leadframe lead includes a first area and a second area adjacent the first area;
roughening a surface of the leadframe lead comprises roughening a surface of both the first area and the second area of the leadframe lead to form a roughened first area surface and a roughened second area surface; and
forming a thin plating layer over the roughened leadframe lead surface comprises forming a thin plating layer over the roughened first area surface but not over the roughened second area surface.
26. An integrated circuit device of claim 25 , wherein:
the second area of the leadframe lead, on which the thin plating layer is not formed, is located at an end of the leadframe lead adjacent the die support area; and
the first area of the leadframe lead, on which the thin plating layer is formed, is located away from the end of the leadframe lead, such that the second area of the leadframe lead is located between the first area of the leadframe lead and the die support area.
27. An integrated circuit device of claim 25 , wherein the method of producing the integrated circuit device comprises applying the molding material over both the first area and second area of the leadframe lead, such that the molding material (a) directly contacts the thin plating layer formed on the first area of the leadframe lead and (b) directly contacts the roughened second area surface of the second area of the leadframe lead, which is free of the thin plating layer.
28. An integrated circuit device of claim 24 , wherein:
the average roughness Ra of the roughened leadframe lead surface is at least 0.150 μm; and
the thickness of the thin plating layer is less than or equal to 3.75 μm.
29. An integrated circuit structure, comprising:
a leadframe comprising:
a die support area; and
a plurality of leadframe leads adjacent the die support area, each leadframe lead including a finger tip area at one end of the leadframe lead;
an integrated circuit die mounted on the die support area of the leadframe;
wherein at least one of the leadframe leads has a roughening leadframe lead surface formed by a roughening process, each roughening leadframe lead surface having three-dimensional contours having an average roughness Ra defined by an average distance from the respective roughened leadframe lead surface to a mean plane of the respective roughened leadframe lead surface, along a direction perpendicular to the mean plane;
a thin plating layer formed over at least a portion of each roughened leadframe lead surface, the thin plating layer on each roughened leadframe lead surface having a thickness of less than 40 times the average roughness Ra of the respective roughened leadframe lead surface, such that each respective thin plating layer is received into the three-dimensional contours of the respective roughened leadframe lead surface and thereby forms a three-dimensionally contoured surface at an outer surface of the respective thin plating layer; and
a molding material formed over the leadframe and integrated circuit die such that the molding material contacts and adheres to the three-dimensionally contoured surface at the outer surface of each thin plating layer.
30. The integrated circuit structure of claim 29 , wherein:
the leadframe lead includes a first area and a second area adjacent the first area;
roughening a surface of the leadframe lead comprises roughening a surface of both the first area and the second area of the leadframe lead to form a roughened first area surface and a roughened second area surface; and
forming a thin plating layer over the roughened leadframe lead surface comprises forming a thin plating layer over the roughened first area surface but not over the roughened second area surface.
31. An integrated circuit device of claim 30 , wherein:
the second area of the leadframe lead, on which the thin plating layer is not formed, is located at an end of the leadframe lead adjacent the die support area; and
the first area of the leadframe lead, on which the thin plating layer is formed, is located away from the end of the leadframe lead, such that the second area of the leadframe lead is located between the first area of the leadframe lead and the die support area.
32. An integrated circuit device of claim 30 , wherein the method of producing the integrated circuit device comprises applying the molding material over both the first area and second area of the leadframe lead, such that the molding material (a) directly contacts the thin plating layer formed on the first area of the leadframe lead and (b) directly contacts the roughened second area surface of the second area of the leadframe lead, which is free of the thin plating layer.
33. An integrated circuit device of claim 29 , wherein:
the average roughness Ra of the roughened leadframe lead surface is at least 0.150 μm; and
the thickness of the thin plating layer is less than or equal to 3.75 μm.