Integrated circuit structure and method for forming the same

1. A method, comprising:

forming a transistor over a front side of a substrate;

forming a front-side interconnect structure over the transistor, the front-side interconnect structure comprising layers of conductive lines, and conductive vias interconnecting the layers of conductive lines;

forming a first bonding layer over the front-side interconnect structure, wherein forming the first bonding layer comprises:

forming a first dielectric layer over the front-side interconnect structure;

performing a first planarization process to the first dielectric layer; and

after performing the first planarization process, forming a second dielectric layer over the first dielectric layer;

forming a second bonding layer over a carrier substrate;

bonding the front-side interconnect structure to the carrier substrate by pressing the first bonding layer against the second bonding layer; and

forming a backside interconnect structure over a backside of the substrate after bonding the front-side interconnect structure to the carrier substrate.

2. The method of claim 1 , further comprising performing a second planarization process to the second dielectric layer prior to bonding the front-side interconnect structure to the carrier substrate.

3. The method of claim 1 , wherein the first dielectric layer after performing the first planarization process is thicker than the second dielectric layer.

4. The method of claim 1 , wherein bonding the front-side interconnect structure to the carrier substrate comprises performing an annealing process.

5. The method of claim 1 , further comprising removing the carrier substrate after forming the backside interconnect structure.

6. The method of claim 1 , further comprising performing a planarization process to the backside of the substrate prior to forming the backside interconnect structure.

7. The method of claim 1 , wherein the first bonding layer and the second bonding layer are made of a same material.

8. The method of claim 1 , further comprising forming a third dielectric layer over the second dielectric layer.

9. A method, comprising:

forming a fin over a front side of a substrate;

forming a gate structure and source/drain structures over the fin;

forming a front-side interconnect structure over the gate structure;

forming a first dielectric layer over the front-side interconnect structure;

performing a first planarization process to the first dielectric layer;

forming a second dielectric layer over the planarized first dielectric layer;

performing a second planarization process to the second dielectric layer;

bonding the front-side interconnect structure to a carrier substrate by using the planarized second dielectric layer; and

forming a backside interconnect structure over a backside of the substrate after bonding the front-side interconnect structure to the carrier substrate.

10. The method of claim 9 , further comprising forming a third dielectric layer over the carrier substrate prior to bonding the front-side interconnect structure to the carrier substrate, wherein bonding the front-side interconnect structure to the carrier substrate is performed by pressing the planarized second dielectric layer against the third dielectric layer.

11. The method of claim 10 , further comprising performing an annealing process after pressing the planarized second dielectric layer against the third dielectric layer.

12. The method of claim 10 , wherein the third dielectric layer is thinner than the planarized first dielectric layer.

13. The method of claim 10 , wherein the third dielectric layer is thinner than the planarized second dielectric layer.

14. The method of claim 9 , wherein the planarized second dielectric layer has a thickness lower than a thickness of the planarized first dielectric layer.

15. The method of claim 9 , wherein the first dielectric layer and the second dielectric layer are made of silicon oxide.

16. A method, comprising:

forming a transistor comprising a gate structure and a source/drain epitaxial structures respectively on opposite sides of the gate structure;

forming a front-side interconnect structure on front-sides of the source/drain epitaxial structures;

forming a backside interconnect structure on backsides of the source/drain epitaxial structures;

forming a supporting substrate separated from the source/drain epitaxial structures at least by the front-side interconnect structure; and

forming a bonding layer bonding the front-side interconnect structure with the supporting substrate, wherein the bonding layer comprises:

a first dielectric layer in contact with the front-side interconnect structure;

a second dielectric layer spaced apart from the front-side interconnect structure by the first dielectric layer, the second dielectric layer being thinner than the first dielectric layer; and

a third dielectric layer between the second dielectric layer and the supporting substrate.

17. The method of claim 16 , wherein the first, second, and third dielectric layer are made of a same material.

18. The method of claim 16 , wherein the second dielectric layer is thicker than the third dielectric layer.

19. The method of claim 16 , wherein the bonding layer further comprises a fourth dielectric layer between the second dielectric layer and the third dielectric layer, wherein the first dielectric layer is thicker than the fourth dielectric layer.

20. The method of claim 19 , wherein the first, second, third, and fourth dielectric layers are made of a same material.