Mixed current-forced read scheme for MRAM array with selector

1. An apparatus, comprising:

a memory array comprising a plurality of memory cells, each memory cell comprising a resistive random access memory element and a two terminal threshold selector element in series with the memory element; and

a control circuit configured to:

read a group of selected memory cells using a current-force referenced read; and

read the group of selected memory cells using a current-force self-referenced read in response to a condition being met for the current-force referenced read.

2. The apparatus of claim 1 , wherein the resistive random access memory element comprises a magnetoresistive random access memory (MRAM) element.

3. The apparatus of claim 1 , wherein the two terminal threshold selector element comprises an Ovonic Threshold Switch (OTS).

4. The apparatus of claim 1 , wherein the memory array comprises:

a plurality of first conductive lines; and

a plurality of second conductive lines, each of the plurality of memory cells are connected between one of the first conductive lines and one of the second conductive lines.

5. The apparatus of claim 1 , wherein the control circuit is configured to:

perform a decoding algorithm on data read from the group of the selected memory cells using the current-force referenced read, wherein the condition comprises a failure to decode data that was read from the group using the current-force referenced read.

6. The apparatus of claim 5 , wherein the control circuit comprises:

an error correction code (ECC) engine on the same semiconductor die as the memory array, the ECC engine configured to perform the decoding algorithm on the data read from the group of the selected memory cells using the current-force referenced read.

7. The apparatus of claim 1 , wherein the control circuit is configured to:

estimate a number of bits that are in error in a codeword read from the group using the current-force referenced read based on a syndrome of the codeword, wherein the condition comprises the number of bits estimated to be in error being greater than a threshold.

8. The apparatus of claim 1 , wherein the condition is based on how many of the memory cells in the group have a resistance that falls into an uncertainty zone between a first resistance distribution and a second resistance distribution.

9. The apparatus of claim 8 , wherein the control circuit is further configured to:

return a result from the current-force self-referenced read of the group in response to a pre-determined number or more of the memory cells being in the uncertainty zone.

10. The apparatus of claim 9 , wherein the control circuit is further configured to:

perform a decoding algorithm on data read from the group of the selected memory cells using the current-force referenced read in response to less than the pre-determined number of memory cells being in the uncertainty zone; and

return a result from the current-force referenced read of the group in response to successfully decoding and correcting the data.

11. The apparatus of claim 1 , wherein the control circuit is configured to:

store results from reading the group using the current-force referenced read;

write the selected memory cells to a known state in the current-force self-referenced read;

force a read current through each respective selected memory cell in the current-force self-referenced read after writing the selected memory cells to the known state; and

compare the stored results with results of forcing the read current through the respective selected memory cells.

12. The apparatus of claim 1 , wherein the control circuit is further configured to:

send, in response to the condition being met for the current-force referenced read, a retry signal to a memory controller that issued a read command for data stored in the group.

13. The apparatus of claim 12 , wherein the control circuit further includes the memory controller, the memory controller configured to re-issue the read command for the data stored in the group after waiting a pre-determined time from receiving the retry signal, the pre-determined time based on how long it will take the control circuit to perform the current-force self-referenced read; and

the control circuit is configured to return data from reading the group using the current-force self-referenced read to the memory controller in response to the re-issued read command.

14. A method, comprising:

forcing a first read current separately through each memory cell of a group of magnetoresistive random access memory (MRAM) cells, including forcing the first read current through an MRAM element and a threshold switching selector of each respective MRAM cell in series;

comparing, for each respective MRAM cell in the group, a first reference voltage and a second reference voltage to a sense voltage that results across the MRAM cell from forcing the first read current through the MRAM;

determining a number of the MRAM cells in the group that have a sense voltage between the first reference voltage and the second reference voltage;

in response to the number being no more than allowed, returning a read result based on comparing, for each respective MRAM cell in the group, a third reference voltage to the sense voltage that results across the MRAM cell from forcing the first read current through the MRAM cell; and

in response to the number being more than allowed:

performing a self-referenced read of each of the MRAM cells in the group, including forcing a second read current through the MRAM element and the threshold switching selector of each respective MRAM cell in series; and

returning a read result based on the self-referenced read of each of the MRAM cells.

15. The method of claim 14 , wherein returning the read result based on comparing, for each respective MRAM cell in the group, the third reference voltage to the sense voltage that results across the MRAM cell from forcing the first read current through the MRAM cells comprises:

performing a decoding algorithm on data read based on the comparing, for each respective MRAM cell in the group, the third reference voltage to the sense voltage that results across the MRAM cell from forcing the first read current through the MRAM cells.

16. A memory system, the system comprising:

a cross-point memory array comprising a plurality of first conductive lines, a plurality of second conductive lines, and a plurality of memory cells, each respective memory cell connected between one of the first conductive lines and one of the second conductive lines, wherein each memory cell comprises a magnetoresistive random access memory (MRAM) element and a threshold switching selector connected in series with the MRAM element; and

a control circuit that:

reads a group of the memory cells using a current-force referenced read in which the control circuit forces a read current through each respective memory cell and samples a voltage that appears across each respective memory cell;

runs an error correction code (ECC) algorithm on data read from the group using the current-force referenced read;

returns first decoded data in response to the ECC algorithm successfully decoding the data read from the group using the current-force referenced read;

performs a self-referenced read of each memory cell in the group in response to the ECC algorithm failing to decode the data read from the group using the current-force referenced read, including forcing a read current through each memory cell in the group;

runs an ECC algorithm on data read from the group using the self-referenced read; and

returns second decoded data in response to successfully decoding the data read from the group using the self-referenced read.

17. The memory system of claim 16 , wherein the control circuit comprises an ECC engine that resides on the same semiconductor die as the cross-point memory array.

18. The memory system of claim 16 , wherein the threshold switching selector comprises an Ovonic Threshold Switch (OTS).