Methods and apparatus for NAND flash memory
Methods and apparatus for memory operations disclosed. In an embodiment, a method is provided for programming multiple-level cells in a memory array. The memory array includes a plurality of planes and each plane includes a plurality of bit lines. The method includes storing multiple data bits in a first group of planes, one data bit per plane. The multiple data bits are stored in bit line capacitances of the first group of planes. The method also includes programming a selected multiple-level cell in a selected plane according to the multiple data bits that are stored in the bit line capacitances of the first group of planes. The selected plane is not one of the first group of planes.
1. A method for programming multiple-level cells in a memory array, wherein the memory array comprises a plurality of planes, and wherein each plane comprises a plurality of bit lines, the method comprising:
storing multiple data bits in a first group of planes, one data bit per plane, wherein the multiple data bits are stored in bit line capacitances of the first group of planes, and wherein the first group of planes is coupled to a first group of page buffers, respectively;
programming a selected multiple-level cell in a selected plane according to the multiple data bits that are stored in the bit line capacitances of the first group of planes, and wherein the selected plane is not one of the first group of planes; and
latching the multiple data bits that are stored in the bit line capacitances of the first group of planes into data latches of the first group of page buffers.
2. The method of claim 1 , wherein the multiple-level cells are configured to have a selected number of levels greater than 2 levels.
3. The method of claim 2 , wherein the multiple data bits represent any number of levels up to a maximum number of levels of the selected multiple-level cell.
4. The method of claim 1 , wherein the multiple data bits comprise three data bits that are stored in three planes of the first group of planes, and wherein the multiple-level cell comprises a TLC cell.
5. The method of claim 1 , wherein the operation of programming comprises:
determining a level from the multiple data bits latched in the data latches of the first group of page buffers; and
programming the level into the selected multiple-level cell in the selected plane.
6. The method of claim 1 , wherein the multiple level cell comprises one of a MLC, TLC, QLC, and PLC cell.
7. A method for programming multiple-level cells in a memory array, wherein the memory array comprises a plurality of banks, and wherein each bank comprises a plurality of multiple-level cells, the method comprising:
storing first data bits in a first selected bank using single level cell programming;
reprogramming the first data bits in the first selected bank to a multiple-level cell in a second selected bank using multiple level cell programming during a first reprogramming time interval; and
storing second data bits in a third selected bank during the first reprogramming time interval using single level cell programming.
8. The method of claim 7 , wherein the first selected bank and the second selected bank are the same bank.
9. The method of claim 7 , wherein the first selected bank, the second selected bank, and the third selected bank are all different banks.
10. The method of claim 7 , wherein the multiple-level cells are configured to have a selected number of levels greater than 2 levels.
11. The method of claim 7 , further comprising simultaneously performing the operations of reprogramming the first data bits and storing the second data bits.
12. The method of claim 7 , further comprising simultaneously performing the operations of:
storing third data bits in the first selected bank using single level cell programming; and
reprogramming the second data bits in the second bank to a multiple-level cell in a four selected bank using multiple level cell programming during a second reprogramming time interval.
13. The method of claim 12 , further comprising simultaneously performing the operations of reprogramming the second data bits and storing the third data bits.
14. The method of claim 13 , further comprising alternating the operations of storing and reprograming between banks.