Formation of gate all around device
Horizontal gate-all-around devices and methods of manufacturing same are described. The hGAA devices comprise an oxide layer and a semiconductor material layer between source regions and drain regions of the device. The method includes growing a conformal epitaxial layer on a nanosheet channel layer, followed by radical plasma oxidation (RPO) to oxidize the conformal epitaxial layer. An alternative method includes growing a conformal epitaxial layer on a nanosheet channel layer, followed by a surface treatment, and then radical plasma oxidation (RPO) to oxidize the conformal epitaxial layer.
1. A method of forming a semiconductor device, the method comprising:
a first pre-cleaning process, comprising pre-cleaning a plurality of nanosheet channel layers, each of the plurality of nanosheet channel layers having a first thickness;
forming a conformal sacrificial epitaxial silicon layer consisting essentially of epitaxial silicon on each of the plurality of nanosheet channel layers;
a second pre-cleaning process, comprising pre-cleaning the plurality of nanosheet channel layers with the conformal sacrificial epitaxial silicon layer thereon to remove native oxide and/or residues; and
oxidizing the conformal sacrificial epitaxial silicon layer using a plasma to form a silicon oxide layer consisting essentially of silicon oxide on each of the plurality of nanosheet channel layers, each of the plurality of nanosheet channel layers having a second thickness, wherein the first thickness and the second thickness are substantially equal.
2. The method of claim 1 , wherein the conformal sacrificial epitaxial silicon layer has a thickness in a range of from about 0.5 nm to about 2.5 nm.
3. The method of claim 1 , wherein the first thickness is in a range of from about 4 nm to about 8 nm.
4. The method of claim 1 , wherein the second thickness is in a range of from about 4 nm to about 8 nm.
5. The method of claim 1 , wherein the second thickness is in a range of from about 2.5 nm to about 7.5 nm.
6. The method of claim 1 , further comprising, prior to the second pre-cleaning process, selectively etching a superlattice structure comprising the plurality of nanosheet channel layers and a corresponding plurality of semiconductor material layers alternatingly arranged in a plurality of stacked pairs to remove each of the plurality of semiconductor material layers to form a plurality of voids in the superlattice structure, the plurality of semiconductor material layers extending between a source region and a drain region.
7. The method of claim 6 , further comprising forming the source region adjacent a first end of the superlattice structure and the drain region adjacent a second opposing end of the superlattice structure.
8. The method of claim 6 , wherein the superlattice structure is formed on a top surface of a substrate.
9. The method of claim 7 , wherein the plurality of semiconductor material layers comprise silicon germanium (SiGe) and the plurality of nanosheet channel layers comprise silicon (Si).
10. The method of claim 6 , wherein the plurality of semiconductor material layers comprise silicon (Si) and the plurality of nanosheet channel layers comprise silicon germanium (SiGe).
11. The method of claim 1 , wherein forming the conformal sacrificial epitaxial silicon layer comprises epitaxially growing the conformal sacrificial epitaxial silicon layer at a temperature in a range of from 500° C. to 800° C.
12. The method of claim 1 , wherein the method is performed in a processing chamber without breaking vacuum.
13. The method of claim 1 , wherein pre-cleaning the plurality of nanosheet channel layers comprises one or more of a dry etch process and a wet etch process.
14. The method of claim 1 , wherein oxidizing the conformal sacrificial epitaxial silicon layer comprises radical plasma oxidation (RPO) of the conformal sacrificial epitaxial silicon layer at a temperature in a range of from about 500° C. to about 900° C. in an atmosphere of hydrogen (H 2 ) gas and oxygen (O 2 ) gas at ambient pressure.
15. The method of claim 1 , further comprising:
forming a high-k dielectric layer on the oxide layer; and
forming a conductive layer on the high-k dielectric layer.
16. A method of forming a semiconductor device, the method comprising:
a first pre-cleaning process, comprising pre-cleaning a plurality of nanosheet channel layers, each of the plurality of nanosheet channel layers having a first thickness;
forming a conformal sacrificial epitaxial silicon layer consisting essentially of epitaxial silicon on each of the plurality of nanosheet channel layers;
annealing the plurality of nanosheet channel layers with the conformal sacrificial epitaxial silicon layer thereon; and
oxidizing the conformal sacrificial epitaxial silicon layer using a plasma to form an oxide layer consisting essentially of silicon oxide on each of the plurality of nanosheet channel layers, each of the plurality of nanosheet channel layers having a second thickness, wherein the first thickness and the second thickness are substantially equal.
17. The method of claim 16 , wherein the conformal sacrificial epitaxial silicon layer has a thickness in a range of from 0.5 nm to 2.5 nm.
18. The method of claim 16 , wherein the first thickness is in a range of from 4 nm to 8 nm.
19. The method of claim 16 , wherein the second thickness is in a range of from 2.5 nm to 10 nm.
20. The method of claim 16 , further comprising, prior to the second pre-cleaning process, selectively etching a superlattice structure comprising the plurality of nanosheet channel layers and a corresponding plurality of semiconductor material layers alternatingly arranged in a plurality of stacked pairs to remove each of the plurality of semiconductor material layers to form a plurality of voids in the superlattice structure, the plurality of semiconductor material layers extending between a source region and a drain region.
21. The method of claim 20 , further comprising forming the source region adjacent a first end of the superlattice structure and the drain region adjacent a second opposing end of the superlattice structure.
22. The method of claim 20 , further comprising forming the superlattice structure on a top surface of a substrate.
23. The method of claim 20 , wherein the plurality of semiconductor material layers comprise silicon germanium (SiGe) and the plurality of nanosheet channel layers comprise silicon (Si).
24. The method of claim 20 , wherein the plurality of semiconductor material layers comprise silicon (Si) and the plurality of nanosheet channel layers comprise silicon germanium (SiGe).
25. The method of claim 16 , wherein forming the conformal sacrificial epitaxial silicon layer comprises epitaxially growing the conformal sacrificial epitaxial silicon layer at a temperature in a range of from 500° C. to 800° C.
26. The method of claim 16 , wherein the method is performed in a processing chamber without breaking vacuum.
27. The method of claim 16 , wherein pre-cleaning the plurality of nanosheet channel layers comprises one or more of a dry etch process and a wet etch process.
28. The method of claim 16 , wherein oxidizing the conformal sacrificial epitaxial silicon layer comprises radical plasma oxidation (RPO) of the conformal sacrificial epitaxial silicon layer at a temperature in a range of from about 500° C. to about 900° C. in an atmosphere of hydrogen (H 2 ) gas and oxygen (O 2 ) gas at ambient pressure.
29. The method of claim 16 , wherein the plurality of nanosheet channel layers are annealed at a temperature in a range of from 600° C. to 900° C. at a pressure in a range of from 5 Torr to 20 Torr in an atmosphere comprising hydrogen (H 2 ).
30. The method of claim 16 , further comprising:
forming a high-k dielectric layer on the oxide layer; and
forming a conductive layer on the high-k dielectric layer.