Input/output (I/O) devices with greater source/drain proximity than non-I/O devices
A semiconductor device includes a first FinFET device and a second FinFET device. The first FinFET device includes a first gate, a first source, and a first drain. The first FinFET device has a first source/drain proximity. The second FinFET device includes a second gate, a second source, and a second drain. The second FinFET device has a second source/drain proximity that is smaller than the first source/drain proximity. In some embodiments, \the first FinFET device is an Input/Output (I/O) device, and the second FinFET device is a non-I/O device such as a core device. In some embodiments, the greater source/drain proximity of the first FinFET device is due to an extra spacer of the first FinFET device that does not exist for the second FinFET device.
1. A semiconductor device, comprising:
a first FinFET device that includes a first gate, a first source, and a first drain, wherein the first FinFET device has a first source/drain proximity; and
a second FinFET device that includes a second gate, a second source, and a second drain, wherein the second FinFET device has a second source/drain proximity that is different from the first source/drain proximity:
wherein:
the first FinFET device and the second FinFET device each include a first spacer that is undoped; and
the first FinFET device, but not the second FinFET device, further includes a second spacer that is doped and that has a different material composition than the first spacer.
2. The semiconductor device of claim 1 , wherein:
the first FinFET device is an Input/Output (I/O) device; and
the second FinFET device is a non-I/O device.
3. The semiconductor device of claim 2 , wherein the non-I/O device is a core device.
4. The semiconductor device of claim 2 , wherein the first source/drain proximity is greater than the second source/drain proximity due to the second spacer.
5. The semiconductor device of claim 2 , wherein:
the second spacer is thicker than the first spacer.
6. The semiconductor device of claim 1 , wherein:
the first spacer contains silicon carbon oxynitride (SiCON) or silicon oxycarbide (SiOC); and
the second spacer contains silicon nitride, silicon oxide, or amorphous silicon.
7. The semiconductor device of claim 6 , wherein the second spacer is doped with carbon or boron.
8. The semiconductor device of claim 1 , wherein the first gate and the second gate each include a high-k gate dielectric and a metal gate electrode.
9. The semiconductor device of claim 1 , wherein:
the first source and first drain are formed within and around a first portion of a first semiconductor layer extending in a first direction; the first gate wraps around a second portion of the first semiconductor layer in a second direction and a third direction; and
the first, second, and third directions are orthogonal to one another.
10. The semiconductor device of claim 1 , wherein the first FinFET device is configured to tolerate a greater amount of current swing or a greater amount of voltage swing than the second FinFET device.
11. A semiconductor device, comprising:
a first FinFET device, that includes a first gate, a first source, and a first drain, wherein a first distance separates the first source from the first drain; and
a second FinFET device that includes a second gate, a second source, and a second drain, wherein a second distance separates the second source from the second drain, and wherein the first distance is greater than the second distance;
wherein:
the first FinFET device and the second FinFET device each include an undoped first spacer; and
the first FinFET device, but not the second FinFET device, further includes a doped second spacer.
12. The semiconductor device of claim 11 , wherein:
the first distance and the second distance are each measured in a first direction; and
the first gate and the second gate each extend in a second direction that is different from the first direction.
13. The semiconductor device of claim 11 , wherein:
the first FinFET device is a part of an Input/Output (I/O) device;
the second FinFET device is a part of a non-I/O device.
14. The semiconductor device of claim 13 , wherein the I/O device is configured to tolerate a greater amount of current swing or a greater amount of voltage swing than the non-I/O device.
15. The semiconductor device of claim 13 , wherein the non-I/O device includes a static random-access memory (SRAM).
16. The semiconductor device of claim 11 , wherein:
the undoped first spacer includes a first material composition; and
the doped second spacer includes a second material composition different from the first material composition.
17. The semiconductor device of claim 16 , wherein:
the first material composition comprises silicon carbon oxynitride (SiCON) or silicon oxycarbide (SiOC); and
the second material composition comprises silicon nitride, silicon oxide, or amorphous silicon.
18. The semiconductor device of claim 16 , wherein the second material is doped with carbon or boron.
19. A semiconductor device, comprising:
a first FinFET device that is a part of an Input/Output (I/O) device, the first FinFET device including a first gate, a first source, and a first drain, wherein a first distance separates the first source from the first drain in an X-direction, and wherein the first gate spans along a Y-direction perpendicular to the X-direction; and
a second FinFET device that is a part of a non-I/O device, the second FinFET device including a second gate, a second source, and a second drain, wherein a second distance separates the second source from the second drain in the X-direction, and wherein the first distance is greater than the second distance;
wherein:
the first FinFET device and the second FinFET device each include an undoped first spacer; and
the first FinFET device, but not the second FinFET device, further includes a doped second spacer that is doped with carbon or boron.
20. The semiconductor device of claim 19 , wherein:
the doped second spacer is thicker than the undoped first spacer.