Granted Patent B2

US 12,651,038 · App. 17/507,185 · Granted Jun 9, 2026

Inventors: Wen Ma (Sunnyvale, CA); Tung Thanh Hoang (San Jose, CA); Martin Lueker-Boden (Fremont, CA)

Assignee: Western Digital Technologies, Inc.

G06F17/16G06G7/16

Abstract

Claims (83)

1 . A non-volatile memory device, comprising:

a control circuit configured to connect to a plurality of non-volatile memory arrays, each of the plurality of non-volatile memory arrays comprising a plurality of programmable resistance memory cells connected between a corresponding word line and a corresponding bit line, the plurality of non-volatile memory arrays configured, individually or in combination, to store positive-valued components of real and imaginary parts of basis values of a discrete Fourier transformation as conductance values and to store negative-valued components of the real and imaginary parts of the basis values as conductance values, the control circuit further configured to:

receive real and imaginary parts of inputs for the discrete Fourier transformation;

perform, using at least one non-volatile memory array of the plurality of non-volatile memory arrays, a first in-memory matrix multiplication between positive-valued components of the real and imaginary parts of the inputs for the discrete Fourier transformation and the positive-valued components of the basis values;

perform, using at least one non-volatile memory array of the plurality of non-volatile memory arrays, a second in-memory matrix multiplication between the positive-valued components of the real and imaginary parts of the inputs and the negative-valued components of the basis values;

perform, using at least one non-volatile memory array of the plurality of non-volatile memory arrays, a third in-memory matrix multiplication between negative-valued components of the real and imaginary parts of the inputs for the discrete Fourier transformation and the positive-valued components of the basis values;

perform, using at least one non-volatile memory array of the plurality of non-volatile memory arrays, a fourth in-memory matrix multiplication between the negative-valued components of the real and imaginary parts of the inputs and the negative-valued components of the basis values;

wherein, to perform the in-memory matrix multiplications, the control circuit is further configured to separately provide to non-volatile memory arrays of the plurality of non-volatile memory arrays: i) the positive-valued components of the real and imaginary parts of the inputs for the first and second in-memory matrix multiplications and ii) the negative-valued components of the real and imaginary parts of the inputs for the third and fourth in-memory matrix multiplications; and

determine real and imaginary parts of outputs of the discrete Fourier transformation of the real and imaginary parts of the inputs from a linear combination of outputs of the first in-memory matrix multiplication, outputs of the second in-memory matrix multiplication, outputs of the third in-memory matrix multiplication, and outputs of the fourth in-memory matrix multiplication.

2 . The non-volatile memory device of claim 1 , wherein the control circuit is formed on a control die, the non-volatile memory device further comprising:

a memory die including one or more of the plurality of non-volatile memory arrays, the memory die formed separately from and bonded to the control die.

3 . The non-volatile memory device of claim 1 , wherein the control circuit is further configured to:

perform the first in-memory matrix multiplication by applying voltage levels corresponding to the positive-valued components of the real and imaginary parts of the inputs to word lines of a first array of the plurality of non-volatile memory arrays, wherein a first portion of the first array is configured to store positive-valued components of the basis values;

perform the second in-memory matrix multiplication by applying the voltage levels corresponding to the positive-valued components of the real and imaginary parts of the inputs to the word lines of the first array, wherein a second portion of the first array is configured to store negative-valued components of the basis values; and

determine the real and imaginary parts of outputs of the discrete Fourier transformation based at least in part from differences between outputs on bit lines of the first portion of the first array and outputs on the bit lines of the second portion of the first array in response to applying the voltage levels corresponding to the positive-valued components of the inputs to the first array.

4 . The non-volatile memory device of claim 3 , wherein the control circuit is further configured to:

determine the real and imaginary parts of outputs of the discrete Fourier transformation from bit line by bit line differences between outputs on the bit lines of the first portion of the first array and outputs on the bit lines of the second portion of the first array.

5 . The non-volatile memory device of claim 1 , wherein the control circuit is further configured to:

perform the first in-memory matrix multiplication using a first array of the plurality of non-volatile memory arrays, the first array configured to store the positive-valued components of the basis values;

perform the second in-memory matrix multiplication using a second array of the plurality of non-volatile memory arrays, the second array configured to store the negative-valued components of the basis values;

perform the third in-memory matrix multiplication using a third array of the plurality of non-volatile memory arrays, the third array configured to store the positive-valued components of the basis values; and

perform the fourth in-memory matrix multiplication using a fourth array of the plurality of non-volatile memory arrays, the fourth array configured to store the negative-valued components of the basis values;

wherein word lines of the first array are connected to word lines of the second array and word lines of the third array are connected to word lines of the fourth array; and

wherein the connected word lines of the first array and the second array are disconnected from the connected word lines of the third array and the fourth array.

6 . The non-volatile memory device of claim 1 , wherein the control circuit is further configured to:

sequentially perform the first in-memory matrix multiplication and the third in-memory matrix multiplication using a first array of the plurality of non-volatile memory arrays, the first array configured to store the positive-valued components of the basis values; and

sequentially perform the second in-memory matrix multiplication and the fourth in-memory matrix multiplication using a second array of the plurality of non-volatile memory arrays, the second array configured to store the negative-valued components of the basis values;

wherein word lines of the first array are connected to word lines of the second array.

7 . The non-volatile memory device of claim 1 , wherein the control circuit comprises:

a digital to analog converter configured to:

receive the real and imaginary parts of the inputs as digital values; and

convert the real and imaginary parts of the positive-valued components of the inputs to corresponding analog values, wherein performing the first and second in-memory matrix multiplications includes applying voltages based on the corresponding analog values, and

an analog to digital converter configured to:

receive analog values for currents on bit lines of a first array and a second array of the plurality of non-volatile memory arrays, the first array configured to store the positive-valued components of the basis values and the second array configured to store the negative-valued components of the basis values; and

convert the outputs of the first in-memory matrix multiplication and the outputs of the second in-memory matrix multiplication to digital values.

8 . The non-volatile memory device of claim 1 , wherein the control circuit is further configured to:

perform the first in-memory matrix multiplication by:

sequentially applying voltage levels corresponding to the positive-valued components of the real and imaginary parts of the inputs to word lines of a first array of the plurality of non-volatile memory arrays, the first array configured to store the positive-valued components of the basis values; and

accumulating outputs from bit lines of the first array in response to sequentially applying the voltage levels to the word lines thereof;

perform the second in-memory matrix multiplication by:

sequentially applying voltage levels corresponding to the positive-valued components of the real and imaginary parts of the inputs to word lines of a second array of the plurality of non-volatile memory arrays, the second array configured to store the negative-valued components of the basis values; and

accumulating outputs from bit lines of the second array in response to sequentially applying the voltage levels to the word lines thereof, and

determine the real and imaginary parts of outputs of the discrete Fourier transformation of the real and imaginary parts of the inputs based at least in part from differences between the accumulated outputs of the first in-memory matrix multiplication and the second matrix multiplication.

9 . The non-volatile memory device of claim 1 ,

wherein each of the programmable resistance memory cells of the plurality of non-volatile memory arrays comprises a resistive random-access memory (ReRAM) device.

10 . The non-volatile memory device of claim 1 ,

wherein each of the programmable resistance memory cells of the plurality of non-volatile memory arrays comprises a magnetic random-access memory (MRAM) device.

11 . A method, comprising:

receiving real and imaginary parts of inputs for a discrete Fourier transformation;

converting positively valued ones of the real and imaginary parts of the inputs into a first set of voltage values;

converting negatively valued ones of the real and imaginary parts of the inputs into a second set of voltage values;

applying the first set of voltage values to one of one or more non-volatile memory arrays storing positively valued ones of basis values for the discrete Fourier transformation to generate a first set of output current values;

applying the first set of voltage values to one of one or more non-volatile memory arrays storing negatively valued ones of the basis values for the discrete Fourier transformation to generate a second set of output current values;

applying the second set of voltage values to one of the one or more non-volatile memory arrays storing the positively valued ones of the basis values to generate a third set of output current values;

applying the second set of voltage values to one of the one or more non-volatile memory arrays storing the negatively valued ones of the basis values to generate a fourth set of output current values;

wherein the first set of voltage values is separately applied from the second set of voltage values; and

determining real and imaginary parts of outputs for the discrete Fourier transformation from a linear combination of the first, second, third, and fourth sets of output current values.

12 . The method of claim 11 , wherein:

in each of applying the first set of voltage values to one of the one or more non-volatile memory arrays storing the positively valued ones of the basis values and one of the one or more non-volatile memory arrays storing the negatively valued ones of the basis values, the first set of voltage values is applied sequentially as a plurality of subsets of the first set of voltage values;

in each of applying the second set of voltage values to one of the one or more non-volatile memory arrays storing the positively valued ones of the basis values and one of the one or more non-volatile memory arrays storing the negatively valued ones of the basis values, the second set of voltage values is applied sequentially as a plurality of subsets of the second set of voltage values; and

determining the real and imaginary parts of outputs is based on accumulated values for the first, second, third, and fourth sets of output current values in response to the sequentially applied subsets of the first and second sets of voltage values.

13 . A non-volatile memory device, comprising:

one or more non-volatile memory arrays, each non-volatile memory array of the one or more non-volatile memory arrays comprising a plurality of programmable resistance non-volatile memory cells, with each programmable resistance non-volatile memory cell connected between a corresponding word line and a corresponding bit line, and the one or more non-volatile memory arrays configured to store components of real and imaginary parts of basis values of a discrete Fourier transformation as conductance values; and

a control circuit configured to connect to the one or more non-volatile memory arrays, the control circuit further configured to:

receive real and imaginary parts of inputs for the discrete Fourier transformation;

convert positively valued real and imaginary parts of the inputs into a first set of voltage values;

convert negatively valued real and imaginary parts of the inputs into a second set of voltage values;

sequentially apply the first set of voltage values and the second set of voltage values to the word lines of the one or more non-volatile memory arrays configured to store components of the basis values;

accumulate outputs from the bit lines of the one or more non-volatile memory arrays in response to applying the first set of voltage values or the second set of voltage values; and

determine real and imaginary parts of an output of the discrete Fourier transformation of the real and imaginary parts of the inputs from the accumulated outputs from the bit lines in response to sequentially applying the first set of voltage values and the second set of voltage values.

14 . The non-volatile memory device of claim 13 , wherein the control circuit is formed on a control die and the one or more non-volatile memory arrays are formed on one or more memory dies formed separately from and bonded to the control die.

15 . The non-volatile memory device of claim 13 , wherein the programmable resistance non-volatile memory cells store components of the real and imaginary parts of a subset of a full set of basis values of the discrete Fourier transformation.

16 . The non-volatile memory device of claim 13 , wherein the control circuit comprises:

a digital to analog converter configured to:

receive the real and imaginary parts of inputs for the discrete Fourier transformation as digital values; and

convert the real and imaginary parts of the inputs for the discrete Fourier transformation to analog values corresponding to the applied voltage levels; and

an analog to digital converter configured to:

receive the outputs from the bit lines of the one or more non-volatile memory arrays as analog values; and

convert the outputs from the bit lines to digital values.

17 . The non-volatile memory device of claim 16 , wherein the control circuit is further configured to convert the outputs from the bit lines to digital values prior to accumulating the outputs.

18 . The non-volatile memory device of claim 16 , wherein the control circuit is further configured to convert the outputs from the bit lines to digital values after accumulating the outputs.

19 . The non-volatile memory device of claim 13 , wherein each of the programmable resistance non-volatile memory cells comprises a resistive random-access memory (ReRAM) device.

20 . The non-volatile memory device of claim 13 , wherein each of the programmable resistance non-volatile memory cells comprises a magnetic random-access memory (MRAM) device.

Assignments (3)

Continuity (1)

References Cited (12)