IP Library › Granted Patent US 12,148,710
Granted Patent B2
US 12,148,710 · App. 17/510,807 · Granted Nov 19, 2024

Three-dimensional memory device containing bridges for enhanced structural support and methods of forming the same

Inventors: Koichi Matsuno (Fremont, CA); Johann Alsmeier (San Jose, CA)
Assignee: SANDISK TECHNOLOGIES LLC
H01L23/544H10B41/27H10B43/27
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Quick Facts
Patent No.
US 12,148,710
App. No.
17/510,807
Granted
Nov 19, 2024
Kind
B2
Abstract

A three-dimensional memory device includes a first alternating stack of first word lines and first insulating layers, first memory stack structures vertically extending through the first alternating stack, a second alternating stack of second word lines and second insulating layers, second memory stack structures vertically extending through the second alternating stack, plural backside trench fill structures located between the first alternating stack and the second alternating stack, and a bridge region located between the plural backside trench fill structures and between the between the first alternating stack and the second alternating stack. At least one insulating layer extends continuously through the first alternating stack, the second alternating stack, and the bridge region.

Claims (40)

1. A three-dimensional memory device, comprising:

a first alternating stack of first word lines and first insulating layers;

first memory stack structures vertically extending through the first alternating stack;

a second alternating stack of second word lines and second insulating layers;

second memory stack structures vertically extending through the second alternating stack;

plural backside trench fill structures located between the first alternating stack and the second alternating stack; and

a bridge region located between the plural backside trench fill structures and between the between the first alternating stack and the second alternating stack, wherein at least one insulating layer extends continuously through the first alternating stack, the second alternating stack, and the bridge region;

wherein:

the first alternating stack comprises a lower first tier, an upper first tier located above the lower first tier, and a first inter-tier region located between the lower and the upper first tiers;

the second alternating stack comprises a lower second tier, an upper second tier located above the lower first tier, and a second inter-tier region located between the lower and the upper second tiers;

a backside trench filled with the plural backside trench fill structures and the bridge region located between the first and the second alternating stacks;

the lower first tier is laterally spaced apart along a second horizontal direction from the lower second tier by a lower portion of the backside trench which extends along a first horizontal direction;

the upper first tier is laterally spaced apart along the second horizontal direction from the upper second tier by an upper portion of the backside trench which extends along the first horizontal direction;

the backside trench fill structures comprise a respective dielectric trench fill material portion;

the at least one insulating layer which extends continuously through the first alternating stack, the second alternating stack, and the bridge region comprises an inter-tier dielectric layer continuously extending through the first inter-tier region, the second inter-tier region and the bridge region;

a portion of the inter-tier dielectric layer located in the bridge region comprises a dielectric bridge portion which extends through an opening between adjacent dielectric trench fill material portions; and

the dielectric bridge portion comprises at least one concave sidewall that contacts a convex sidewall segment of an adjacent one of the dielectric trench fill material portions; and

further comprising an additional inter-tier dielectric layer continuously extending through the first and the second inter-tier regions and comprising an additional dielectric bridge portion that laterally extends through the bridge region through an opening between adjacent dielectric trench fill material portions.

2. The three-dimensional memory device of claim 1 , further comprising a dielectric inter-tier etch stop liner layer contacting a bottom surface of the inter-tier dielectric layer, contacting a top surface of the additional inter-tier dielectric layer, and continuously extending through the first alternating stack, the second alternating stack, and the bridge region.

3. The three-dimensional memory device of claim 1 , further comprising an inter-tier electrically conductive layer contacting a bottom surface of the inter-tier dielectric layer, contacting a top surface of the additional inter-tier dielectric layer, and continuously extending through the first alternating stack, the second alternating stack, and the bridge region.

4. A three-dimensional memory device, comprising:

a first alternating stack of first word lines and first insulating layers;

first memory stack structures vertically extending through the first alternating stack;

a second alternating stack of second word lines and second insulating layers;

second memory stack structures vertically extending through the second alternating stack;

plural backside trench fill structures located between the first alternating stack and the second alternating stack; and

a bridge region located between the plural backside trench fill structures and between the between the first alternating stack and the second alternating stack, wherein at least one insulating layer extends continuously through the first alternating stack, the second alternating stack, and the bridge region;

wherein:

the first alternating stack comprises a lower first tier, an upper first tier located above the lower first tier, and a first inter-tier region located between the lower and the upper first tiers;

the second alternating stack comprises a lower second tier, an upper second tier located above the lower first tier, and a second inter-tier region located between the lower and the upper second tiers;

a backside trench filled with the plural backside trench fill structures and the bridge region located between the first and the second alternating stacks;

the lower first tier is laterally spaced apart along a second horizontal direction from the lower second tier by a lower portion of the backside trench which extends along a first horizontal direction;

the upper first tier is laterally spaced apart along the second horizontal direction from the upper second tier by an upper portion of the backside trench which extends along the first horizontal direction;

the backside trench fill structures comprise a respective dielectric trench fill material portion;

the at least one insulating layer which extends continuously through the first alternating stack, the second alternating stack, and the bridge region comprises an inter-tier dielectric layer continuously extending through the first inter-tier region, the second inter-tier region and the bridge region;

a portion of the inter-tier dielectric layer located in the bridge region comprises a dielectric bridge portion which extends through an opening between adjacent dielectric trench fill material portions; and

the dielectric bridge portion comprises at least one concave sidewall that contacts a convex sidewall segment of an adjacent one of the dielectric trench fill material portions; and

wherein the dielectric bridge portion comprises:

a first vertically-straight and laterally-concave sidewall segment having a first radius of curvature in a plan view; and

a pair of second vertically-straight and laterally-concave sidewall segments having a second radius of curvature that is greater than the first radius of curvature in the plan view and adjoined to vertically-extending edges of the first vertically-straight and laterally-concave sidewall segment.

Assignments (4)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 31, 2024
From: SANDISK TECHNOLOGIES LLC
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 069796/0423 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 26, 2021
From: MATSUNO, KOICHI; ALSMEIER, JOHANN
To: SANDISK TECHNOLOGIES LLC
Reel/Frame 057915/0870 →
Continuity (2)
Continuation In Part 17174064 · Feb 11, 2021
Related Publication 20220254728A1 · Aug 11, 2022