Dielectric reflow for boundary control
Embodiments of the invention include a dielectric reflow technique for boundary control in which a first layer is deposited on a first transistor region and a second transistor region, the first and second transistor regions being adjacent. A dielectric layer is formed to protect the second transistor region such that the first transistor region is exposed, the dielectric layer bounded at a first location. In response to removing a portion of the first layer on the first transistor region, the dielectric layer protecting the second transistor region is reflowed such that at least a reflowed portion of the dielectric layer extends beyond the first location.
1. A method comprising:
depositing a first layer on a first transistor region and a second transistor region, the first and second transistor regions being adjacent;
forming a dielectric layer to protect the second transistor region such that the first transistor region is exposed, the dielectric layer bounded at a first location;
removing a portion of the first layer on the first transistor region such that the portion removed undercuts the dielectric layer and leaves a gap under the dielectric layer; and
reflowing the dielectric layer protecting the second transistor region such that at least a reflowed portion of the dielectric layer extends beyond the first location and fills in the gap.
2. The method of claim 1 , wherein the reflowed portion extends beyond the first location toward the first transistor region.
3. The method of claim 1 , wherein the reflowed portion at least covers a footing of the first layer on the second transistor region.
4. The method of claim 1 , wherein the first layer is deposited over channel structures in the first and second transistor regions.
5. The method of claim 1 further comprising removing a remainder of the first layer on the first transistor region.
6. The method of claim 1 further comprising:
removing the dielectric layer, responsive to removing a remainder of the first layer on the first transistor region; and
depositing a second layer on the first and second transistor regions.
7. The method of claim 1 , wherein the first transistor region corresponds to an n-type field-effect transistor (NFET).
8. The method of claim 1 , wherein the second transistor region corresponds to a p-type field-effect transistor (PFET).
9. The method of claim 1 , wherein the first layer comprises a p-type work function material.
10. The method of claim 1 , wherein a second layer is applied to the first and second transistor regions, the second layer comprising an n-type work function material.