Metal hard mask integration for active device structures
A semiconductor structure comprises an active device stack comprising one or more layers, the one or more layers comprising a top electrode. The semiconductor structure also comprises an additional layer disposed over the active device stack, an encapsulation layer surrounding the active device stack and the additional layer, and a contact to the top electrode coupled to the additional layer.
1 . A semiconductor structure comprising:
an active device stack comprising one or more layers, the one or more layers comprising a top electrode;
an additional layer disposed over the active device stack;
an encapsulation layer surrounding the active device stack and the additional layer; and
a contact to the top electrode coupled to the additional layer;
wherein the additional layer and the contact comprise a first material; and
wherein the top electrode comprises a second material different than the first material.
2 . The semiconductor structure of claim 1 , wherein the additional layer comprises a protection layer.
3 . The semiconductor structure of claim 1 , wherein the second material comprises titanium nitride.
4 . The semiconductor structure of claim 1 , wherein the first material comprises copper and the second material comprises titanium nitride.
5 . The semiconductor structure of claim 1 , wherein the active device stack comprises a pillar for a non-volatile memory device.
6 . The semiconductor structure of claim 5 , wherein the non-volatile memory device comprises a resistive random-access memory device, wherein the one or more layers of the active device stack further comprise a bottom electrode and an insulator disposed over the bottom electrode, and wherein the top electrode is disposed over the insulator.
7 . An integrated circuit, comprising:
a non-volatile memory device structure comprising:
a non-volatile memory device stack comprising one or more layers, the one or more layers comprising a top electrode;
an additional layer disposed over the non-volatile memory device stack;
an encapsulation layer surrounding the non-volatile memory device stack and the additional layer; and
a contact to the top electrode coupled to the additional layer;
wherein the additional layer and the contact comprise a first material; and
wherein the top electrode comprises a second material different than the first material.
8 . The integrated circuit of claim 7 , wherein the additional layer comprises a protection layer.
9 . The integrated circuit of claim 7 , wherein the second material comprises titanium nitride.
10 . The integrated circuit of claim 7 , wherein the first material comprises copper and the second material comprises titanium nitride.
11 . The integrated circuit of claim 7 , wherein the non-volatile memory device structure comprises a resistive random-access memory device, and wherein the one or more layers of the non-volatile memory device stack further comprise a bottom electrode and an insulator disposed over the bottom electrode, and wherein the top electrode is disposed over the insulator.
12 . The semiconductor structure of claim 1 , wherein the first material comprises a metal material.
13 . The semiconductor structure of claim 1 , wherein the first material comprises one of copper, ruthenium, tungsten and cobalt.
14 . The semiconductor structure of claim 1 , wherein the second material comprises one of tantalum nitride, tungsten, tungsten nitride and ruthenium.
15 . The integrated circuit of claim 7 , wherein the first material comprises a metal material.
16 . The integrated circuit of claim 7 , wherein the first material comprises one of copper, ruthenium, tungsten and cobalt.
17 . The integrated circuit of claim 7 , wherein the second material comprises one of tantalum nitride, tungsten, tungsten nitride and ruthenium.