Integrated circuit including connection line
An integrated circuit includes: a first cell arranged in a first row extending in a first direction and performing a first function, a second cell arranged in the first row and performing a second function, a third cell arranged in a second row extending in the first direction and performing the first function, a fourth cell arranged in the second row and performing the second function, a first connection line connecting a first via in the first cell to a second via in the second cell, and a second connection line connecting a third via in the third cell to a fourth via in the fourth cell, wherein a length of the first connection line is different from a length of the second connection line.
1 . An integrated circuit comprising:
a first cell arranged in a first row extending in a first direction and performing a first function;
a second cell arranged in the first row and performing a second function;
a third cell arranged in a second row extending in the first direction and performing the first function;
a fourth cell arranged in the second row and performing the second function;
a first connection line connecting a first via in the first cell to a second via in the second cell; and
a second connection line connecting a third via in the third cell to a fourth via in the fourth cell,
wherein each of the first cell, the second cell, the third cell, and the fourth cell is a standard cell configured to provide one of a Boolean logic function or a storage function,
wherein a first length of the first connection line corresponds to a sum of twice a minimum enclosure distance according to an enclosure rule, a first width of the first via, a second width of the second via, and a first distance between the first via and the second via,
wherein the first length is greater than a minimum length of a wiring line according to a design rule,
wherein a second length of the second connection line corresponds to the minimum length, and
wherein the second length is shorter than a sum of twice the minimum enclosure distance according to the enclosure rule, a third width of the third via, a fourth width of the fourth via, and a second distance between the third via and the fourth via.
2 . The integrated circuit of claim 1 , further comprising:
a fifth cell arranged in a third row extending in the first direction and performing a third function;
a sixth cell arranged in a fourth row extending in the first direction and performing a fourth function;
a seventh cell arranged in the third row and performing the third function;
an eighth cell arranged in the fourth row and performing the fourth function;
a third connection line connecting a fifth via in the fifth cell to a sixth via in the sixth cell and extending in a second direction perpendicular to the first direction; and
a fourth connection line connecting a seventh via in the seventh cell to an eighth via in the eighth cell and extending in the second direction,
wherein a length of the third connection line is different from a length of the fourth connection line.
3 . The integrated circuit of claim 2 , wherein the length of the third connection line corresponds to a sum of twice the minimum enclosure distance according to the enclosure rule, a width of the fifth via in the second direction, a width of the sixth via in the second direction, and a distance between the fifth via and the sixth via.
4 . The integrated circuit of claim 3 , wherein the length of the third connection line is greater than the minimum length of the wiring line according to the design rule.
5 . The integrated circuit of claim 3 , wherein the length of the fourth connection line corresponds to the minimum length of the wiring line according to the design rule.
6 . The integrated circuit of claim 5 , wherein the length of the fourth connection line is shorter than the length of the third connection line.
7 . The integrated circuit of claim 1 , wherein the first cell and the second cell have the same Front End Of Line (FEOL) structure.
8 . The integrated circuit of claim 1 ,
wherein the first cell includes N first gate electrodes adjacent to each other in the first direction and extending in a second direction perpendicular to the first direction, and the third cell includes N second gate electrodes adjacent to each other in the first direction and extending in the second direction, where N is a natural number, and
wherein the first via is electrically connected to an M-th first gate electrode among the N first gate electrodes, and the third via is electrically connected to an M-th second gate electrode among the N second gate electrodes, where M is a natural number.
9 . The integrated circuit of claim 1 ,
wherein the first cell includes K first source/drain regions adjacent to each other in the first direction, and the third cell includes K second source/drain regions adjacent to each other in the first direction, where K is a natural number, and
wherein the first via is electrically connected to an L-th first source/drain region among the K first source/drain regions, and the third via is electrically connected to an L-th second source/drain region among the K second source/drain regions, where L is a natural number.
10 . An integrated circuit comprising:
a first cell including a first via;
a second cell including a second via;
a third cell including a third via;
a fourth cell including a fourth via;
a first connection line extending in a first direction and connecting the first via to the second via; and
a second connection line extending in the first direction and connecting the third via to the fourth via,
wherein a first length of the first connection line corresponds to a sum of twice a minimum enclosure distance representing a region extending from an enclosure of each of the first via and the second via, a first width of the first via, a second width of the second via, and a first via distance between the first via and the second via,
wherein the first length is greater than a minimum length of a wiring line according to a design rule,
wherein a second length of the second connection line corresponds to the minimum length,
wherein the second length is shorter than a sum of twice the minimum enclosure distance, a third width of the third via, a fourth width of the fourth via, and a second via distance between the third via and the fourth via, and
wherein each of the first cell, the second cell, the third cell, and the fourth cell is a standard cell configured to provide one of a Boolean logic function or a storage function.
11 . A method of designing an integrated circuit, the method comprising:
placing a first cell including a first pin having a length determined based on a first width of a first via and a minimum enclosure distance according to an enclosure rule, based on input data defining the integrated circuit;
placing a second cell including a second pin having a length determined based on a second width of a second via and the minimum enclosure distance, based on the input data;
placing a third cell including a third pin;
placing a fourth cell including a fourth pin;
connecting the first pin to the second pin by using a first connection line extending in a first direction;
connecting the third pin to the fourth pin by using a second connection line extending in the first direction; and
generating output data defining a layout of the integrated circuit,
wherein a first length of the first connection line corresponds to a sum of twice the minimum enclosure distance according to the enclosure role, the first width of the first via, the second width of the second via, and a first distance between the first via and the second via,
wherein the first length is greater than a minimum length of a wiring line according to a design rule,
wherein a second length of the second connection line corresponds to the minimum length,
wherein the second length is shorter than a sum of twice the minimum enclosure distance according to the enclosure rule, a third width of the third via, a fourth width of the fourth via, and a second distance between the third via and the fourth via, and
wherein each of the first cell, the second cell, the third cell, and the fourth cell is a standard cell configured to provide one of a Boolean logic function or a storage function.
12 . The method of claim 11 , wherein the first connection line extends in the first direction or extends in a second direction perpendicular to the first direction.