Packaging architecture with patterned through-dielectric vias and redistribution layers
A microelectronic assembly is provided, comprising: a first plurality of integrated circuit (IC) dies in a first layer; a second plurality of IC dies in a second layer; and a third plurality of IC dies in a third layer, in which: the second layer is between the first layer and the third layer, an interface between two adjacent layers comprises interconnects having a pitch of less than 10 micrometers between adjacent ones of the interconnects, and each of the first layer, the second layer, and the third layer comprises a dielectric material, and further comprises conductive traces in the dielectric material.
1 . A microelectronic assembly, comprising:
a first plurality of integrated circuit (IC) dies in a first layer;
a second plurality of IC dies in a second layer; and
a third plurality of IC dies in a third layer,
wherein:
the second layer is between the first layer and the third layer,
an interface between the first layer and the second layer comprises die-to-die interconnects having a pitch of less than 10 micrometers between adjacent ones of the die-to-die interconnects, and
each of the first layer, the second layer, and the third layer comprises a dielectric material and conductive traces in the dielectric material, wherein a first conductive trace in the first layer extends in a direction parallel to the interface between the first layer and the second layer, and a second conductive trace in the first layer is between the first conductive trace and the second layer.
2 . The microelectronic assembly of claim 1 , wherein the first conductive trace is coupled to one or more of inductors, transformers, capacitors, and resistors in the dielectric material.
3 . The microelectronic assembly of claim 1 , wherein the first conductive trace comprises a power plane.
4 . The microelectronic assembly of claim 1 , wherein the first conductive trace is an electrical signal trace.
5 . The microelectronic assembly of claim 1 , wherein the dielectric material comprises a compound of silicon and at least one of oxygen, carbon, and nitrogen.
6 . The microelectronic assembly of claim 1 , further comprising a through-dielectric vias (TDVs) in the dielectric material to electrically couple the first conductive trace with at least one of the second plurality of IC dies.
7 . The microelectronic assembly of claim 1 , wherein the die-to-die interconnects comprise hybrid bonds between one of the first plurality of IC dies in the first layer and one of the second plurality of IC dies in the second layer.
8 . The microelectronic assembly of claim 1 , wherein the conductive traces in the dielectric material further comprise a third conductive trace in the second layer, wherein the third conductive trace extends in a direction parallel to the interface between the first layer and the second layer.
9 . The microelectronic assembly of claim 1 , wherein the first conductive trace extends through an entire thickness of the first layer.
10 . The microelectronic assembly of claim 1 , wherein the first conductive trace is coupled to a first through-dielectric via (TDV) in the first layer and a second TDV in the first layer.
11 . An IC package, comprising:
a first IC die in a first layer;
a second IC die in a second layer;
a first conductive trace in the first layer, wherein the first conductive trace extends through an entire thickness of the first layer;
a second conductive trace in the second layer; and
a package substrate coupled to the first layer,
wherein:
an interface between the first layer and the second layer comprises die-to-die interconnects having a pitch of less than 10 micrometers between adjacent ones of the die-to-die interconnects, the interface extending along a plane, wherein the first conductive trace extends in a direction parallel to the plane;
the first layer and the second layer comprise dielectric material, and
through-dielectric vias (TDVs), the first conductive trace, and the second conductive trace are in the dielectric material.
12 . The IC package of claim 11 , wherein the dielectric material comprises a compound of silicon and at least one of oxygen, carbon, and nitrogen.
13 . The IC package of claim 11 , wherein a first portion of the TDVs are configured for power distribution between the first IC die and the package substrate, and TDVs in the first portion are larger than TDVs in a second portion of the TDVs.
14 . The IC package of claim 11 , wherein the first conductive trace and the second conductive trace are electrical signal traces for routing signals between the first IC die and the second IC die.
15 . The IC package of claim 11 , wherein one of the TDVs couples the first conductive trace with the package substrate.
16 . The IC package of claim 11 , wherein the die-to-die interconnects comprise first interconnects, and the IC package further comprises a third IC die in a third layer, the third layer coupled to the second layer with second interconnects having a pitch of less than 10 micrometers between adjacent ones of the second interconnects.
17 . The IC package of claim 16 , wherein one of the TDVs is configured to electrically couple the third IC die with a third conductive trace.
18 . The IC package of claim 16 , wherein the TDVs are configured to electrically couple the third layer with the first layer.
19 . The IC package of claim 11 , wherein the second conductive trace extends in a second direction parallel to the plane.
20 . The IC package of claim 11 , further comprising a third conductive trace in the second layer, wherein the third conductive trace is between the first conductive trace and the second layer.