Etch stop layer for backside processing architecture
An integrated circuit structure includes a first layer comprising silicon and at least one of carbon, oxygen, or hydrogen, and a device layer including a plurality of transistors above the first layer. A first interconnect structure is above the device layer and includes first conductive interconnect features. A second interconnect structure is below the first layer and includes second conductive interconnect features. In an example, one or more of the second conductive interconnect features pass through a bottom surface of the first layer. One or more third conductive interconnect features vertically extend through the device layer to a top surface of the first layer. In an example, the one or more third conductive interconnect features are in contact with the corresponding one or more of the second conductive interconnect features that pass through the bottom surface of the first layer.
1 . An integrated circuit device comprising:
a first layer comprising silicon and at least one of carbon, oxygen, or hydrogen;
a device layer including a plurality of transistors and a dielectric region, the dielectric region being directly on a top surface of the first layer;
a first interconnect structure above the device layer and including one or more first interconnect layers, the one or more first interconnect layers including first conductive interconnect features;
a second interconnect structure below the device layer and the first layer, the second interconnect structure including one or more second interconnect layers, the one or more second interconnect layers including second conductive interconnect features, wherein one or more of the second conductive interconnect features pass through a bottom surface of the first layer, the one or more second conductive interconnect features having a first width measured at or near a top surface of the one or more second conductive interconnect features that is less than a second width of the one or more second conductive interconnect features that is measured at or near a bottom surface of the one or more second conductive interconnect features; and
one or more third conductive interconnect features vertically extending through the dielectric region of the device layer to the top surface of the first layer, the one or more third conductive interconnect features in direct contact with the corresponding one or more of the second conductive interconnect features that pass through the bottom surface of the first layer, the one or more third conductive interconnect features having a third width measured at or near a top surface of the one or more third conductive interconnect features that is greater than a fourth width of the one or more third conductive interconnect features that is measured at or near a bottom surface of the one or more third conductive interconnect features.
2 . The integrated circuit device of claim 1 , wherein the first conductive interconnect features route signals between the plurality of transistors.
3 . The integrated circuit device of claim 1 , wherein the second conductive interconnect features route signals (i) between the plurality of transistors and (ii) from or to one or more input or output (I/O) pins that are below the second interconnect structure.
4 . The integrated circuit device of claim 1 , wherein the second conductive interconnect features route power to the plurality of transistors.
5 . The integrated circuit device of claim 1 , wherein the first layer has a thickness in the range of 3-20 nm, where the thickness is measured between the device layer and a top one of the one or more second interconnect layers.
6 . The integrated circuit device of claim 1 , wherein the first layer comprises carbon and at least one of oxygen or hydrogen.
7 . The integrated circuit device of claim 1 , wherein the one or more third conductive interconnect features include first and second deep conductive vias, each deep conductive via connected to one or more of the transistors by a corresponding conductor of the device layer.
8 . The integrated circuit device of claim 1 , wherein the one or more second conductive interconnect features include a buried or backside power rail (BPR) to transmit power to a terminal of a transistor of the plurality of transistors.
9 . The integrated circuit device of claim 1 , wherein at least one of the first conductive interconnect features comprises conductive material, and a barrier layer separating the conductive material from adjacent dielectric material of a corresponding one of the one or more first interconnect layers.
10 . The integrated circuit device of claim 1 , wherein at least one of the second conductive interconnect features comprises conductive material, and a barrier layer separating the conductive material from adjacent dielectric material of a corresponding one of the one or more second interconnect layers.
11 . The integrated circuit device of claim 1 , wherein:
at least one of the third conductive interconnect features comprises conductive material;
the integrated circuit further comprises a barrier layer on walls of the at least one of the third conductive interconnect features; and
a bottom surface of a section of the barrier layer on a bottom wall of the at least one of the third conductive interconnect features is coplanar with a top surface of the first layer.
12 . The integrated circuit device of claim 11 , wherein:
the barrier layer comprises one or more of cobalt, nickel, ruthenium, molybdenum, manganese, titanium, tungsten, tantalum, nitrogen, silicon; and
the conductive material comprises one or more of copper, ruthenium, molybdenum, tin, indium, antimony, aluminum, or bismuth.
13 . An integrated circuit device comprising:
a layer comprising silicon and carbon;
a dielectric region directly on a top surface of the layer;
a first interconnect feature extending vertically through the dielectric region to the top surface of the layer, wherein the first interconnect feature is tapered towards a bottom of the first interconnect feature, such that a first width of the first interconnect feature measured at or near a top surface of the first interconnect feature is at least 5% greater than a second width of the first interconnect feature measured at or near a bottom surface of the first interconnect feature; and
a second interconnect feature below the layer and passing through a bottom surface of the layer,
wherein the first interconnect feature is in direct contact with the second interconnect feature,
wherein the second interconnect feature is tapered towards a top of the second interconnect feature, such that a third width of the second interconnect feature measured at or near a top surface of the second interconnect feature is at least 5% less than a fourth width of the second interconnect feature measured at or near a bottom surface of the second interconnect feature, and
wherein the first, second, third, and fourth widths are measured in a horizontal direction that is parallel to a length of the layer.
14 . The integrated circuit device of claim 13 , further comprising:
a first barrier layer on walls of the first interconnect feature, and a second barrier layer on walls of the second interconnect feature,
wherein the first barrier layer of the first interconnect feature and the second barrier layer of the second interconnect feature are in direct contact with each other.
15 . The integrated circuit device of claim 14 , wherein the bottom surface of the first barrier layer is directly on the top surface of the second barrier layer.
16 . The integrated circuit device of claim 13 , wherein the layer comprises at least one of oxygen or hydrogen.
17 . The integrated circuit device of claim 13 , further comprising:
a device layer comprising a plurality of transistors, wherein the dielectric region is part of the device layer.
18 . An integrated circuit, comprising:
a device layer comprising one or more semiconductor devices and a dielectric region;
a material layer below the device layer, such that the dielectric region is directly on a top surface of the material layer, the material layer comprising silicon and at least one of carbon, oxygen, or hydrogen;
a first conductive structure extending through an entire thickness of the dielectric region; and
a second conductive structure extending through at least a portion of a thickness of the material layer, wherein a bottom surface of the first conductive structure directly contacts a top surface of the second conductive structure, wherein a width at the top surface of the second conductive structure is less than a width of a bottom surface of the second conductive structure, and wherein a width at a top surface of the first conductive structure is greater than a width at the bottom surface of the first conductive structure.
19 . The integrated circuit of claim 18 , wherein the material layer comprises carbon and at least one of oxygen or hydrogen.
20 . The integrated circuit of claim 18 , wherein the material layer has a thickness in the range of 3-20 nm.