Memory device and method of manufacturing the same

1. A memory device comprising:

interlayer insulation layers spaced apart from each other and stacked;

gate lines formed between the interlayer insulation layers; and

a plug vertically passing through the interlayer insulation layers and the gate lines,

wherein each of the gate lines comprises:

a barrier layer formed along an inner wall of each of the interlayer insulation layers and the plug;

a first conductive layer surrounded by the barrier layer; and

a second conductive layer surrounded by the first conductive layer, wherein a material of the second conductive layer is different from a material of the first conductive layer, and wherein a size of the second conductive layer is variable along a direction in which the gate lines extend,

wherein the material of the second conductive layer has a melting point lower than the material of the first conductive layer.

2. The memory device of claim 1 , wherein the barrier layer comprises titanium nitride (TIN).

3. The memory device of claim 1 , wherein the first conductive layer comprises tungsten (W).

4. The memory device of claim 1 , wherein the material of the second conductive layer has a crystal structure smaller than the material of the first conductive layer.

5. The memory device of claim 1 , wherein the material of the second conductive layer is recrystallized by a heat treatment process.

6. The memory device of claim 1 , wherein the material of the second conductive layer comprises molybdenum (Mo).

7. The memory device of claim 1 , wherein the plug comprises:

a blocking layer vertically passing through the interlayer insulation layers and the gate lines;

a charge trap layer formed along an inner wall of the blocking layer;

a tunnel insulation layer formed along an inner wall of the charge trap layer;

a channel layer formed along an inner wall of the tunnel insulation layer; and

a core insulation layer filling a space surrounded by the channel layer.

8. A memory device comprising:

interlayer insulation layers and gate lines alternately stacked on each other;

plugs vertically passing through the interlayer insulation layers and the gate lines; and

a first slit separating the interlayer insulation layers and the gate lines to separate different memory blocks,

wherein each of the gate lines includes:

a barrier layer;

a first conductive layer surrounded by the barrier layer; and

a second conductive layer surrounded by the first conductive layer, wherein a size of the second conductive layer increases with decreasing distance of the second conductive layer from the first slit,

wherein a material of the second conductive layer has a melting point lower than a material of the first conductive layer.

9. The memory device of claim 8 , wherein the first conductive layer comprises tungsten (W).

10. The memory device of claim 8 , wherein the material of the second conductive layer has a crystal structure smaller than the material of the first conductive layer.

11. The memory device of claim 8 , wherein the second conductive layer comprises molybdenum.

12. The memory device of claim 8 , wherein the size of the second conductive layer is based on a thickness of each of the gate lines.

13. The memory device of claim 8 , further comprising:

a gate separation trench separating each of some gate lines adjacent to bit lines among the gate lines, when the plugs contact the bit lines and a source line.

14. The memory device of claim 13 , wherein the gate separation trench is formed along a direction perpendicular to a direction in which the bit lines extend.

15. The memory device of claim 13 , wherein the size of the second conductive layer decreases with decreasing distance to the gate separation trench.

16. The memory device of claim 8 , further comprising:

a second slit spaced apart from the first slit.

17. The memory device of claim 16 , wherein the size of the second conductive layer increases with decreasing distance to the first slit or the second slit, and decreases with decreasing distance to a center between the first and second slits.

18. The memory device of claim 16 , wherein the size of the second conductive layer is symmetrical with respect to a center between the first and second slits.

19. A method of manufacturing a memory device, the method comprising:

alternately stacking interlayer insulation layers and sacrificial layers on a lower structure;

forming plugs vertically passing through the interlayer insulation layers and the sacrificial layers;

forming a slit vertically passing through the interlayer insulation layers and the sacrificial layers in a boundary area between different memory blocks;

removing the sacrificial layers exposed through a sidewall of the slit;

forming a first conductive layer in an area from which the sacrificial layers are removed; and

filling a void generated when the first conductive layer is formed with a second conductive layer, wherein a material of the second conductive layer is different from a material of the first conductive layer,

wherein the material of the second conductive layer has a melting point lower than the material of the first conductive layer.

20. The method of claim 19 , wherein the first conductive layer comprises tungsten (W).

21. The method of claim 19 , wherein the material of the second conductive layer has a crystal structure smaller than the material of the first conductive layer.

22. The method of claim 19 , wherein the material of the second conductive layer is recrystallized by a heat treatment process.

23. The method of claim 19 , wherein the material of the second conductive layer comprises molybdenum (Mo).

24. The method of claim 19 , wherein a source gas for forming the second conductive layer is supplied through the slit.

25. The method of claim 19 , further comprising:

performing a heat treatment process to further deform a crystal structure of the second conductive layer to a smaller size, after filling the void generated when the first conductive layer is formed with the second conductive layer.