Memory system including the semiconductor memory and a controller
According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes first blocks including a memory cell capable of storing data of one bit, a second block including a memory cell capable of storing data of two or more bits. The semiconductor memory stores first data in a first latch circuit, and second data in a second latch circuit, and writes the first data into one of the first blocks in page units, and the second data into one of the first blocks in page units. The semiconductor memory writes data of at least two pages into the second block, using the first data stored in the first latch circuit and the second data stored in the second latch circuit.
1. A memory system comprising:
a semiconductor memory configured to store data; and
a controller configured to control the semiconductor memory,
wherein the semiconductor memory includes:
a plurality of first blocks each including a memory cell configured to store data of at least one bit,
a second block including a memory cell configured to store data of two or more bits, and
a sense amplifier including a first latch circuit and a second latch circuit,
wherein data is written into the semiconductor memory in units of a page by both a first write operation and a second write operation,
wherein in the first write operation,
the controller outputs a first write command specifying first data, a second write command specifying second data, and a third write command,
the semiconductor memory writes the first data into a first one of the first blocks, and the second data into a second one of the first blocks, and when receiving the third write command, the semiconductor memory writes data of at least two pages into the second block, using the first data and the second data,
wherein in the second write operation,
after issuing the third write command, the controller issues a first read command, a second read command, and a fourth write command, and
the semiconductor memory: reads the first data from the first one of the first blocks to the first latch circuit in response to the first read command; reads the second data from the second one of the first blocks to the second latch circuit in response to the second read command; and overwrites data of at least two pages in the second block written by the first write operation in response to the fourth write command, using the first data and the second data that are read to the first latch circuit and the second latch circuit, respectively,
wherein the fourth write command corresponds to a word line selected in response to the third write command,
a verify voltage that is used when the data of at least two pages is written in response to the fourth write command is higher than a verify voltage that is used when the data of at least two pages is written in response to the third write command, and
each of the first data and the second data includes each of a first bit and a second bit of the data of two or more bits to be written in the memory cell of the second block.
2. The system according to claim 1 , wherein
the first latch circuit is associated in advance with the first bit, and the second latch circuit is associated in advance with the second bit.
3. The system according to claim 1 , wherein, if data writing to the first one and/or the second one of the first blocks in response to the first write command and/or the second write command fails, the controller does not issue the third write command.
4. The system according to claim 1 , wherein
the controller is configured to issue a status read command to recognize a result of data writing in the semiconductor memory after the controller issues the third write command,
if the data writing to the second block in response to the third write command fails, the controller is configured to specify a different address of the second block and re-issue the third write command.
5. The system according to claim 4 , wherein
if the data writing to the first one and/or the second one of the first blocks in response to the first write command and/or the second write command fails, the controller is configured to specify a different address in the first one and/or the second one of the first blocks and re-outputs the set of the first data and the first write command and; or the set of the second data and the second write command.
6. The system according to claim 1 , wherein the first one of the first blocks is same as the second one of the first blocks.
7. The system according to claim 1 , wherein the first data and the second data are written into same one of the first blocks.
8. The system according to claim 1 , wherein the first one of the first blocks is different from the second one of the first blocks.
9. The system according to claim 1 , wherein
a plurality of memory cells are serially connected to form a serial connection in the first blocks and the second block,
one of the memory cells at one end of the serial connection is connected to a source line, and one of the memory cells at the other end of the serial connection is connected to a bit line,
the bit line is connected to the sense amplifier, and
the second write operation for a first memory cell is executed after the first write operation for a second memory cell that is adjacent to the first memory cell on a side of the bit line.
10. The system according to claim 1 , wherein the second write operation is performed without receiving write data from the controller.
11. The system according to claim 1 , wherein the sense amplifier further includes a third latch circuit to store data received from the controller, and
the overwriting the data to the second block in the second write operation is performed without use of the third latch circuit.
12. The system according to claim 1 , wherein a threshold value of a memory cell targeted for data write is increased by overwriting the data into the second block in the second write operation.