Edge-aligned template structure for integrated circuit packages
Integrated circuit assemblies can be fabricated on a wafer scale, wherein a base template, having a plurality of openings, may cover a base substrate, such as a die wafer, wherein the base substrate has a plurality of first integrated circuit devices formed therein and wherein at least one second integrated circuit device is electrically attached to a corresponding first integrated circuit device through a respective opening in the base template. Thus, when the base substrate and base template are singulated into individual integrated circuit assemblies, the individual integrated circuit assemblies will each have a first integrated circuit that is edge aligned to a singulated portion of the base template. The singulated portion of the base template can provide an improved thermal path, mechanical strength, and/or electrical paths for the individual integrated circuit assemblies.
1. An apparatus, comprising:
a first integrated circuit device having a first surface, an opposing second surface, and at least one side extending between the first surface and the second surface, wherein the at least one side defines a periphery of the first integrated circuit device;
a template structure having a first surface, an opposing second surface, at least one side extending between the first surface and the second surface, and at least one opening extending between the first surface and the second surface, wherein the at least one side defines a periphery of the template structure, wherein the first surface of the template structure is attached to the first surface of the first integrated circuit device; wherein the periphery of the first integrated circuit device is substantially planar with the periphery of the template structure, and wherein the template structure includes at least one through-template via; and
at least one second integrated circuit device within the opening of the template structure, wherein the at least one second integrated circuit device is electrically attached to the first surface of the first integrated circuit device.
2. The apparatus of claim 1 , wherein the at least one second integrated circuit device has a first surface and an opposing second surface, wherein the first surface of the at least one second integrated circuit device is electrically attached to the first surface of the first integrated circuit device, and wherein the at least one second integrated circuit device has a circuit region at the first surface thereof and at least one through-silicon vias extending from the circuit region to the second surface of the at least one second integrated circuit device.
3. The apparatus of claim 2 , wherein the second surface of the at least one second integrated circuit device is substantially planar to the second surface of the template structure.
4. The apparatus of claim 2 , further comprising at least one interconnect electrically attached to the at least one through-silicon vias.
5. The apparatus of claim 1 , further including a fill material disposed between the template structure and the at least one second integrated circuit device.
6. The apparatus of claim 5 , further including a barrier layer between the fill material and the opening of the template structure and between the fill material and the at least one second integrated circuit device.
7. The apparatus of claim 1 , further comprising at least one interconnect electrically attached to the at least one through-template via.
8. An apparatus, comprising:
a package substrate;
a first integrated circuit device having a first surface, an opposing second surface, and at least one side extending between the first surface and the second surface, and wherein the at least one side defines a periphery of the first integrated circuit device;
a template structure having a first surface, an opposing second surface, at least one side extending between the first surface and the second surface, and at least one opening extending between the first surface and the second surface, wherein the template structure includes at least one through-template via, wherein the at least one side defines a periphery of the template structure, wherein the first surface of the template structure is electrically attached to the first surface of the first integrated circuit device and electrically attached to the package, and wherein the periphery of the first integrated circuit device is substantially planar with the periphery of the template structure; and
at least one second integrated circuit device within the opening of the template structure, wherein the at least one second integrated circuit device is electrically attached to the first surface of the first integrated circuit device and electrically attached to the package substrate.
9. The apparatus of claim 8 , wherein the at least one second integrated circuit device has a first surface and an opposing second surface, wherein the first surface of the at least one second integrated circuit device is electrically attached to the first surface of the first integrated circuit device, and wherein the at least one second integrated circuit device has a circuit region at the first surface thereof and at least one through-silicon vias extending from the circuit region to the second surface of the at least one second integrated circuit device.
10. The apparatus of claim 9 , wherein the second surface of the at least one second integrated circuit device is substantially planar to the second surface of the template structure.
11. The apparatus of claim 9 , further comprising at least one interconnect electrically attached to the at least one through-silicon vias.
12. The apparatus of claim 8 , further including a fill material disposed between the template structure and the at least one second integrated circuit device.
13. The apparatus of claim 12 , further including a barrier layer between the fill material and the opening of the template structure and between the fill material and the at least one second integrated circuit device.
14. The apparatus of claim 8 , further comprising at least one interconnect electrically attached to the at least one through-template via.
15. A system, comprising:
an electronic board; and
an integrated circuit package electrically attached to the electronic board, wherein the integrated circuit package comprises:
a package substrate;
a first integrated circuit device having a first surface, an opposing second surface, and at least one side extending between the first surface and the second surface, and wherein the at least one side defines a periphery of the first integrated circuit device;
a template structure having a first surface, an opposing second surface, at least one side extending between the first surface and the second surface, and at least one opening extending between the first surface and the second surface, wherein the template structure includes at least one through-template via, wherein the at least one side defines a periphery of the template structure, wherein the first surface of the template structure is electrically attached to the first surface of the first integrated circuit device and electrically attached to the package, and wherein the periphery of the first integrated circuit device is substantially planar with the periphery of the template structure; and
at least one second integrated circuit device within the opening of the template structure, wherein the at least one second integrated circuit device is electrically attached to the first surface of the first integrated circuit device and electrically attached to the package substrate.
16. The system of claim 15 , wherein the at least one second integrated circuit device has a first surface and an opposing second surface, wherein the first surface of the at least one second integrated circuit device is electrically attached to the first surface of the first integrated circuit device, and wherein the at least one second integrated circuit device has a circuit region at the first surface thereof and at least one through-silicon vias extending from the circuit region to the second surface of the at least one integrated circuit.
17. The system of claim 16 , wherein the second surface of the at least one second integrated circuit device is substantially planar to the second surface of the template structure.
18. The system of claim 16 , further comprising at least one interconnect electrically attached to the at least one through-silicon vias and to the at least one through-template via.
19. The system of claim 15 , further including a fill material disposed between the template structure and the at least one second integrated circuit device.
20. The system of claim 19 , further including a barrier layer between the fill material and the opening of the template structure and between the fill material and the at least one second integrated circuit device.