Three-dimensional dynamic random-access memory (3D DRAM) gate all-around (GAA) design using stacked Si/SiGe
Methods of forming a three-dimensional dynamic random-access memory (3D DRAM) structure are provided herein. In some embodiments, a method of forming a 3D DRAM structure includes forming at least one wordline feature in a first stack comprising a plurality of crystalline silicon (c-Si) layers alternating with a plurality of crystalline silicon germanium (c-SiGe) layers, wherein the wordline feature comprises: vertically etching a first pattern of holes; filling the first pattern of holes with a silicon germanium fill; vertically etching a plurality of isolation slots through the first stack; filling the plurality of isolation slots with a dielectric material to form an isolation layer between the silicon germanium fill; etching the silicon germanium fill and the plurality of c-SiGe layers to form a plurality of gate silicon channels comprising portions of the plurality of c-Si layers; and depositing a layer of conductive material that wraps around the plurality of gate silicon channels.
1 . A method of forming a three-dimensional dynamic random-access memory (3D DRAM) structure, comprising:
forming at least one wordline feature in a first stack comprising a plurality of crystalline silicon (c-Si) layers alternating with a plurality of crystalline silicon germanium (c-SiGe) layers, wherein the wordline feature comprises:
vertically etching a first pattern of holes through the first stack;
filling the first pattern of holes with a silicon germanium fill having a concentration of germanium similar to a concentration of germanium in the plurality of c-SiGe layers;
vertically etching a plurality of isolation slots through the first stack, splitting the silicon germanium fill in each of the first pattern of holes;
filling the plurality of isolation slots with a dielectric material to form an isolation layer between the silicon germanium fill;
etching the silicon germanium fill and the plurality of c-SiGe layers to form a plurality of gate silicon channels comprising portions of the plurality of c-Si layers; and
depositing a layer of conductive material that wraps around the plurality of gate silicon channels.
2 . The method of claim 1 , further comprising depositing the first stack onto a substrate using a heteroepitaxy process.
3 . The method of claim 1 , further comprising depositing a gate dielectric layer around the plurality of gate silicon channels prior to depositing the layer of conductive material.
4 . The method of claim 1 , wherein the silicon germanium fill comprises amorphous silicon germanium deposited via a chemical vapor deposition (CVD) process.
5 . The method of claim 1 , further comprising forming a bitline feature through the first stack extending between rows of the first pattern of holes.
6 . The method of claim 5 , wherein forming the bitline feature comprises:
etching a bitline slit through the first stack;
performing a lateral etch of the plurality of c-Si layers from the bitline slit to expose source/drain doping regions of the 3D DRAM structure; and
depositing a metal layer in at least a portion of a region where the plurality of c-Si layers are laterally etched from the bitline slit.
7 . The method of claim 1 , further comprising forming a plurality of capacitor features in the first stack.
8 . The method of claim 7 , wherein forming the plurality of capacitor features comprises:
etching a capacitor slit through the first stack;
performing a lateral etch of the plurality of c-Si layers from the capacitor slit to expose source/drain doping regions of the 3D DRAM structure; and
depositing a metal electrode layer in at least a portion of a region where the plurality of c-Si layers are laterally etched from the capacitor slit.
9 . The method of claim 1 , further comprising etching the plurality of c-Si layers to widen a gap between the plurality of c-Si layers.
10 . A method of forming a three-dimensional dynamic random-access memory (3D DRAM) structure, comprising:
forming a wordline feature in a first stack comprising a plurality of crystalline silicon (c-Si) layers alternating with a plurality of crystalline silicon germanium (c-SiGe) layers, wherein the wordline feature comprises:
vertically etching a first pattern of holes through the first stack;
filling the first pattern of holes with a silicon germanium fill having a concentration of germanium similar to a concentration of germanium in the plurality of c-SiGe layers;
vertically etching a plurality of isolation slots through the first stack, splitting the silicon germanium fill in each of the first pattern of holes;
filling the plurality of isolation slots with a dielectric material to form an isolation layer between the silicon germanium fill;
etching the silicon germanium fill and the plurality of c-SiGe layers to form a plurality of gate silicon channels comprising portions of the plurality of c-Si layers; and
depositing a layer of conductive material that wraps around the plurality of gate silicon channels;
forming a bitline feature through the first stack extending between rows of the first pattern of holes; and
forming a plurality of capacitor features in the first stack.
11 . The method of claim 10 , further comprising depositing a gate dielectric layer around the plurality of gate silicon channels and depositing a liner layer on the gate dielectric layer prior to depositing the layer of conductive material.
12 . The method of claim 10 , wherein the silicon germanium fill comprises amorphous silicon germanium deposited via a chemical vapor deposition (CVD) process.
13 . The method of claim 10 , wherein forming the bitline feature comprises:
etching a bitline slit through the first stack;
performing a lateral etch of the plurality of c-SiGe layers from the bitline slit;
depositing bitline isolation layers in recesses formed by the lateral etch of the plurality of c-SiGe layers;
performing a lateral etch of the plurality of c-Si layers from the bitline slit to expose source/drain doping regions of the 3D DRAM structure; and
depositing a metal layer in at least a portion of a region where the plurality of c-Si layers are laterally etched from the bitline slit.
14 . The method of claim 10 , wherein forming the plurality of capacitor features comprises:
etching a capacitor slit through the first stack;
performing a lateral etch of the plurality of c-SiGe layers from the capacitor slit;
depositing capacitor isolation layers in recesses formed by the lateral etch of the plurality of c-SiGe layers;
performing a lateral etch of the plurality of c-Si layers from the capacitor slit to expose source/drain doping regions of the 3D DRAM structure; and
depositing a metal electrode layer in at least a portion of a region where the plurality of c-Si layers are laterally etched from the capacitor slit.