Semiconductor device and method of manufacturing the same
View Patent ↗In a method of manufacturing a semiconductor device, the semiconductor device includes a non-volatile memory formed in a memory cell area and a ring structure area surrounding the memory cell area. In the method, a protrusion of a substrate is formed in the ring structure area. The protrusion protrudes from an isolation insulating layer. A high-k dielectric film is formed, thereby covering the protrusion and the isolation insulating layer. A poly silicon film is formed over the high-k dielectric film. The poly silicon film and the high-k dielectric film are patterned. Insulating layers are formed over the patterned poly silicon film and high-k dielectric film, thereby sealing the patterned high-k dielectric film.
1. A semiconductor device including:
a first ring structure disposed over a substrate; and
a frame shaped silicon structure, wherein:
the first ring structure includes:
a first isolation insulating layer disposed in a first trench formed in the substrate at one side of the frame shaped silicon structure;
a first frame shaped poly silicon layer;
a first dielectric layer disposed between the first frame shaped poly silicon layer and the frame shaped silicon structure and between the first frame shaped poly silicon layer and the first isolation insulating layer; and
first sidewall spacers formed on sides of the first frame shaped poly silicon layer, and
a top of the frame shaped silicon layer is higher than a top of the first isolation insulating layer.
2. The semiconductor device of claim 1 , further comprising a second ring structure surrounding the first ring structure, wherein:
the second ring structure includes:
a second isolation insulating layer disposed in a second trench formed in the substrate at another side of the frame shaped silicon structure;
a second frame shaped poly silicon layer;
a second dielectric layer disposed between the second frame shaped poly silicon layer and the frame shaped silicon structure and between the second frame shaped poly silicon layer and the second isolation insulating layer; and
second sidewall spacers formed on sides of the second frame shaped poly silicon layer.
3. The semiconductor device of claim 2 , wherein the top of the frame shaped silicon layer is higher than a top of the second isolation insulating layer.
4. The semiconductor device of claim 3 , wherein the top of the second isolation insulating layer is located at a different level from the top of the first isolation insulating layer.
5. The semiconductor device of claim 3 , wherein the top of the second isolation insulating layer is higher than the top of the first isolation insulating layer.
6. The semiconductor device of claim 2 , wherein the first and second dielectric layers are made of a high-k dielectric material.
7. The semiconductor device of claim 6 , wherein the high-k dielectric material is made of an oxide of at least one element selected from the group consisting of Y, Ta, Ti, Al and Zr.
8. The semiconductor device of claim 6 , wherein the high-k dielectric material is made of hafnium oxide.
9. A semiconductor device comprising:
a frame shaped silicon structure disposed over a substrate;
a first isolation insulating layer disposed over the substrate; and
a first ring structure including a first frame shaped poly silicon layer, wherein
the first ring structure is disposed on a first step between the frame shaped silicon structure and the first isolation insulating layer.
10. The semiconductor device of claim 9 , further comprising:
a second ring structure including a second frame shaped poly silicon layer and disposed over the substrate, wherein
the second ring structure disposed on a second step between the frame shaped silicon structure disposed over the substrate and a second isolation insulating layer.
11. The semiconductor device of claim 10 , wherein a step height of the first step is different from a step height of the second step.
12. The semiconductor device of claim 10 , wherein an upper surface of the second ring structure has a step.
13. The semiconductor device of claim 10 , further comprising:
a third ring structure including a third frame shaped poly silicon layer and disposed over the substrate, wherein
the third ring structure disposed on a third step between the substrate and the second isolation insulating layer.
14. The semiconductor device of claim 13 , wherein an upper surface of the third ring structure has a step.
15. The semiconductor device of claim 13 , wherein a top of the frame shaped silicon structure is located at a same level as an upper surface of the substrate.
16. The semiconductor device of claim 9 , wherein an upper surface of the first ring structure has a step.
17. A semiconductor device including:
a memory formed in a memory cell area of a substrate;
a logic circuit formed in a logic circuit area of the substrate;
a frame shaped silicon structure surrounding the memory cell area and disposed over the substrate, and
a first ring structure including a first frame shaped poly silicon layer, surrounding the memory cell area and separating the memory cell area from the logic circuit area,
wherein the first ring structure is disposed on a first step between the frame shaped silicon structure and a first isolation insulating layer.
18. The semiconductor device of claim 17 , further comprising a second ring structure including a second frame shaped poly silicon layer, surrounding the memory cell area and separating the memory cell area from the logic circuit area,
wherein the second ring structure disposed on a second step between the frame shaped silicon structure disposed over the substrate and a second isolation insulating layer.
19. The semiconductor device of claim 18 , wherein a step height of the first step is different from a step height of the second step.
20. The semiconductor device of claim 19 , further comprising:
a third ring structure including a third frame shaped poly silicon layer, surrounding the logic circuit area and disposed over the substrate,
wherein the third ring structure disposed on a third step between the substrate and the second isolation insulating layer.