IP Library Granted Patent US 11,626,439
Granted Patent B2
US 11,626,439 · App. 17/582,279 · Granted Apr 11, 2023

Imaging device and electronic device

Inventors: Takayuki Ikeda (Kanagawa, JP); Naoto Kusumoto (Kanagawa, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
H01L27/14625H01L27/1207H01L27/1225H01L27/1229H01L27/1469H01L27/14601H01L27/14612H01L27/14616H01L27/14634H01L27/14636H01L27/14643H01L27/14689H01L27/14692H01L29/78H01L29/7869H01L2224/80895H01L2224/80896
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Quick Facts
Patent No.
US 11,626,439
App. No.
17/582,279
Granted
Apr 11, 2023
Kind
B2
Abstract

An imaging device having a three-dimensional integration structure is provided. A first structure including a transistor including silicon in an active layer or an active region and a second structure including an oxide semiconductor in an active layer are fabricated. After that, the first and second structures are bonded to each other so that metal layers included in the first and second structures are bonded to each other; thus, an imaging device having a three-dimensional integration structure is formed.

Claims (50)

1. A camera module comprising:

an image sensor chip;

a wire electrically connected to the image sensor chip;

a lens provided over the image sensor chip; and

a lens cover fixing the lens,

wherein the image sensor chip comprises:

a photoelectric conversion element;

an insulating layer over the photoelectric conversion element;

a light-blocking layer including tungsten over the insulating layer;

a color filter over the light-blocking layer;

a microlens over the color filter;

a first transistor, a second transistor, a third transistor and a fourth transistor, each including silicon in a channel formation region; and

a first metal part and a second metal part, each including copper,

wherein the first metal part is electrically connected to the second metal part provided below the first metal part,

wherein the first transistor and the second transistor are provided over the first metal part,

wherein the third transistor and the fourth transistor are provided below the second metal part,

wherein the first transistor and the second transistor has a shared region in which one of a source region and a drain region of the first transistor is shared with one of a source region and a drain region of the second transistor,

wherein the shared region is configured to be a floating diffusion (FD) node, and is overlapped with a connection region of the first metal part and the second metal part,

wherein a gate of the first transistor is electrically connected to a first wiring,

wherein the first transistor is configured to transmit a charge generated in the photoelectric conversion element to the floating diffusion (FD) node in accordance with a signal of the first wiring,

wherein an anode of the photoelectric conversion element is provided on a light-receiving surface side,

wherein the anode of the photoelectric conversion element is electrically connected to a second wiring, and

wherein the second wiring is provided on a same layer as the first wiring.

2. The camera module according to claim 1 , further comprising a capacitor electrically connected to the floating diffusion (FD) node.

3. An electronic device including the camera module according to claim 1 .

4. A camera module comprising:

an image sensor chip;

a wire electrically connected to the image sensor chip;

a lens provided over the image sensor chip; and

a lens cover fixing the lens,

wherein the image sensor chip comprises:

a photoelectric conversion element;

an insulating layer over the photoelectric conversion element;

a light-blocking layer including tungsten over the insulating layer;

a color filter over the light-blocking layer;

a microlens over the color filter;

a first transistor, a second transistor, a third transistor and a fourth transistor, each including silicon in a channel formation region; and

a first metal part and a second metal part, each including copper,

wherein the first metal part is electrically connected to the second metal part provided below the first metal part,

wherein the first transistor and the second transistor are provided over the first metal part,

wherein the third transistor and the fourth transistor are provided below the second metal part,

wherein the first transistor and the second transistor has a shared region in which one of a source region and a drain region of the first transistor is shared with one of a source region and a drain region of the second transistor,

wherein the shared region is configured to be a floating diffusion (FD) node, and is overlapped with a connection region of the first metal part and the second metal part,

wherein a gate of the first transistor is electrically connected to a first wiring,

wherein the first transistor is configured to transmit a charge generated in the photoelectric conversion element to the floating diffusion (FD) node in accordance with a signal of the first wiring,

wherein an anode of the photoelectric conversion element is provided on a light-receiving surface side, and has a depressed region,

wherein the anode of the photoelectric conversion element is electrically connected to a second wiring through the depressed region, and

wherein the second wiring is provided on a same layer as the first wiring.

5. The camera module according to claim 4 , further comprising a capacitor electrically connected to the floating diffusion (FD) node.

6. An electronic device including the camera module according to claim 4 .

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 24, 2022
From: IKEDA, TAKAYUKI; KUSUMOTO, NAOTO
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 058741/0812 →
Priority Claims (2)
JP 2015-256138 · Dec 28, 2015 · national
JP 2016-171454 · Sep 2, 2016 · national
Continuity (5)
Continuation 17157152 · Jan 25, 2021
Continuation 16541292 · Aug 15, 2019
Continuation 15947911 · Apr 9, 2018
Division 15383327 · Dec 19, 2016
Related Publication 20220149100A1 · May 12, 2022