3D semiconductor device and structure
A 3D semiconductor device, the device including: a first level, where the first level includes a first layer, the first layer including first transistors, and where the first level includes a second layer, the second layer including first interconnections; a second level overlaying the first level, where the second level includes a third layer, the third layer including second transistors, and where the second level includes a fourth layer, the fourth layer including second interconnections; a plurality of connection paths, where the plurality of connection paths provide first connections from a plurality of the first transistors to a plurality of the second transistors, where the second level is bonded to the first level, where the bonded includes oxide to oxide bond regions, where the bonded includes metal to metal bond regions, where the third layer includes crystalline silicon, and where the second level includes a plurality of capacitors.
1. A 3D semiconductor device, the device comprising:
a first level,
wherein said first level comprises a first layer, said first layer comprising first transistors, and
wherein said first level comprises a second layer, said second layer comprising first interconnections;
a second level overlaying said first level,
wherein said second level comprises a third layer, said third layer comprising second transistors, and
wherein said second level comprises a fourth layer, said fourth layer comprising second interconnections;
a plurality of connection paths,
wherein said plurality of connection paths provide first connections from a plurality of said first transistors to a plurality of said second transistors,
wherein said second level is bonded to said first level,
wherein said bonded comprises oxide to oxide bond regions,
wherein said bonded comprises metal to metal bond regions,
wherein said third layer comprises crystalline silicon, and
wherein said second level comprises a plurality of capacitors.
2. The device according to claim 1 ,
wherein said second level comprises at least one scan-chain to support circuit test.
3. The device according to claim 1 , further comprising:
at least one temperature sensor; and
a power control circuit,
wherein said power control circuit is electrically connected to said at least one temperature sensor.
4. The device according to claim 1 ,
wherein said second level comprises at least one charge trap circuit.
5. The device according to claim 1 ,
wherein said second level comprises at least one power regulator circuit.
6. The device according to claim 1 ,
wherein said second level comprises at least one memory array,
wherein said first level comprises at least one control circuit, and
wherein said at least one control circuit controls read operations of said at least one memory array.
7. The device according to claim 1 ,
wherein said second level comprises at least one electrostatic-discharge (“ESD”) circuit.
8. A 3D semiconductor device, the device comprising:
a first level,
wherein said first level comprises a first layer, said first layer comprising first transistors, and
wherein said first level comprises a second layer, said second layer comprising first interconnections;
a second level overlaying said first level,
wherein said second level comprises a third layer, said third layer comprising second transistors, and
wherein said second level comprises a fourth layer, said fourth layer comprising second interconnections;
a plurality of connection paths,
wherein said plurality of connection paths provide first connections from a plurality of said first transistors to a plurality of said second transistors,
wherein said second level is bonded to said first level,
wherein said bonded comprises oxide to oxide bond regions,
wherein said bonded comprises metal to metal bond regions, and
wherein said third layer comprises crystalline silicon; and
at least one test circuit,
wherein said at least one test circuit is capable of performing tests of at least part of said second transistors or said second interconnections.
9. The device according to claim 8 ,
wherein said second level comprises at least one array of memory cells,
wherein said memory cells are volatile type memory cells.
10. The device according to claim 8 ,
wherein said second level comprises at least one phase-lock-loop (“PLL”) circuit.
11. The device according to claim 8 ,
wherein said first level comprises a first computer bus,
wherein said second level comprises a second computer bus, and
wherein said at least one of said plurality of connection paths provides connection between said first bus and said second bus.
12. The device according to claim 8 ,
wherein said first level comprises a first clock-tree,
wherein said second level comprises a second clock-tree, and
wherein said metal to metal bond regions comprise second connections between said first clock-tree and said second clock-tree.
13. The device according to claim 8 ,
wherein said second level comprises at least one electrostatic-discharge (“ESD”) circuit.
14. The device according to claim 8 ,
wherein at least one of said second transistors is a FinFET type transistor.
15. A 3D semiconductor device, the device comprising:
a first level,
wherein said first level comprises a first layer, said first layer comprising first transistors,
wherein said first level comprises first crystalline silicon, and
wherein said first level comprises a second layer, said second layer comprising first interconnections overlaying said first layer;
a second level overlaying said first level,
wherein said second level comprises a third layer, said third layer comprises second crystalline silicon,
wherein said second level is bonded to said first level, and
wherein said bonded comprises oxide to oxide bond regions;
a third level, said third level disposed underneath said first layer,
wherein said third level comprises a plurality of metal conductors; and
a plurality of connection paths,
wherein said plurality of connection paths provide connections from a plurality of said first transistors to said plurality of metal conductors.
16. The device according to claim 15 ,
wherein said plurality of connection paths comprise through said first layer vias, and
wherein at least one of said through said first layer vias has a diameter size of less than 450 nm.
17. The device according to claim 15 ,
wherein at least one of said first transistors comprise at least two side gates.
18. The device according to claim 15 ,
wherein said first level comprises guard-rings, and
wherein at least one of said guard-rings surrounds said first transistors and said first interconnections.
19. The device according to claim 15 ,
wherein said first crystalline silicon thickness is less than 2 microns.
20. The device according to claim 15 ,
wherein said third level comprises at least two metal layers.