IP Library › Granted Patent US 12,363,933
Granted Patent B2
US 12,363,933 · App. 17/591,413 · Granted Jul 15, 2025

Dielectric structures in semiconductor devices

Inventors: Chien-Hung Lin (Hsinchu, TW); Ko-Feng Chen (Hsinchu, TW); Keng-Chu Lin (Ping-Tung, TW)
H10D30/024H01L21/30604H01L21/762H10D30/62H10D62/115H10D62/118
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Quick Facts
Patent No.
US 12,363,933
App. No.
17/591,413
Granted
Jul 15, 2025
Kind
B2
Abstract

A semiconductor device with densified dielectric structures and a method of fabricating the same are disclosed. The method includes forming a fin structure, forming an isolation structure adjacent to the fin structure, forming a source/drain (S/D) region on the fin structure, depositing a flowable dielectric layer on the isolation structure, converting the flowable dielectric layer into a non-flowable dielectric layer, performing a densification process on the non-flowable dielectric layer, and repeating the depositing, converting, and performing to form a stack of densified dielectric layers surrounding the S/D region.

Claims (45)

1. A method, comprising:

forming a fin structure;

forming an isolation structure adjacent to the fin structure;

forming a source/drain (S/D) region on the fin structure;

depositing a flowable dielectric layer on the isolation structure;

converting the flowable dielectric layer into a non-flowable dielectric layer;

performing a planarization process on the non-flowable dielectric layer;

performing a densification process on the non-flowable dielectric layer after performing the planarization process; and

repeating the depositing, converting, and performings to form a stack of densified dielectric layers surrounding the S/D region.

2. The method of claim 1 , wherein depositing the flowable dielectric layer comprises exposing the isolation structure to a silicon- and carbon-containing precursor with carbon-carbon double bonds (C═C).

3. The method of claim 1 , wherein depositing the flowable dielectric layer comprises exposing the isolation structure to oxygen and nitrogen radicals.

4. The method of claim 1 , wherein depositing the flowable dielectric layer comprises exposing the isolation structure to oxygen and ammonia radicals.

5. The method of claim 1 , wherein converting the flowable dielectric layer into the non-flowable dielectric layer comprises performing an inductively coupled plasma treatment with helium, hydrogen, argon, or nitrogen plasma on the flowable dielectric layer.

6. The method of claim 1 , wherein converting the flowable dielectric layer into the non-flowable dielectric layer comprises:

generating a plasma of helium, hydrogen, argon, or nitrogen in an inductively coupled plasma chamber; and

exposing the flowable dielectric layer to the plasma.

7. The method of claim 1 , wherein performing the densification process on the non-flowable dielectric layer comprises performing an annealing process on the non-flowable dielectric layer at a temperature of about 400° C. to about 700° C.

8. The method of claim 1 , wherein performing the densification process on the non-flowable dielectric layer comprises performing an annealing process on the non-flowable dielectric layer in an ambient of steam, hydrogen, argon, carbon-dioxide, nitrogen, or helium.

9. The method of claim 1 , wherein performing the planarization process comprises performing a wet etch process on the non-flowable dielectric layer prior to performing the densification process.

10. The method of claim 1 , wherein performing the planarization process comprises exposing the non-flowable dielectric layer to a dilute hydrofluoric acid solution prior to performing the densification process.

11. A method, comprising:

forming a fin structure on a substrate;

forming a source/drain (S/D) region on the fin structure;

forming a gate structure on the fin structure;

forming a contact structure through the substrate and on a back-side surface of the S/D region;

removing the substrate to expose a back-side surface of the gate structure;

depositing a flowable dielectric layer on the back-side surface of the gate structure;

converting the flowable dielectric layer into a non-flowable dielectric layer; and

performing a densification process on the non-flowable dielectric layer.

12. The method of claim 11 , wherein depositing the flowable dielectric layer comprises exposing the back-side surface of the gate structure to a silicon- and carbon-containing precursor with carbon-carbon double bonds (C═C).

13. The method of claim 11 , wherein converting the flowable dielectric layer into the non-flowable dielectric layer comprises performing an inductively coupled plasma treatment with helium, hydrogen, argon, or nitrogen plasma on the flowable dielectric layer.

14. The method of claim 11 , wherein performing the densification process on the non-flowable dielectric layer comprises performing an annealing process on the non-flowable dielectric layer at a temperature of about 200° C. to about 400° C.

15. The method of claim 11 , wherein performing the densification process on the non-flowable dielectric layer comprises performing an annealing process on the non-flowable dielectric layer in an ambient of steam, hydrogen, argon, carbon-dioxide, nitrogen, or helium.

16. The method of claim 11 , further comprising forming a nitride layer along the back-side surface of the gate structure prior to depositing the flowable dielectric layer.

17. A semiconductor device, comprising:

a stack of nanostructured channel regions;

a gate structure surrounding each of the nanostructured channel regions;

a source/drain (S/D) region adjacent to the gate structure;

a first contact structure on a front-side surface of the S/D region;

a second contact structure on a back-side surface of the S/D region;

a first interlayer dielectric (ILD) layer surrounding the first contact structure and the S/D region, wherein the first ILD layer comprises a stack of first and second dielectric layers; and

a second ILD layer surrounding the second contact structure and on a back-side surface of the gate structure.

18. The semiconductor device of claim 17 , wherein each of the first and second dielectric layers comprises a carbon concentration of about 30 atomic % to about atomic 50%, a silicon concentration of about 20 atomic % to about 30 atomic %, an oxygen concentration of about 25 atomic % to about 40 atomic %, and a nitrogen concentration of about 1 atomic % to about atomic %.

19. The semiconductor device of claim 17 , wherein each of the first and second dielectric layers comprises a density of about 2.1 gm/cm 3 to about 4 gm/cm 3 .

20. The semiconductor device of claim 17 , wherein carbon and oxygen concentrations are greater in the first and second dielectric layers than carbon and oxygen concentrations at an interface between the first and second dielectric layers.

Assignments (2)
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE NAME PREVIOUSLY RECORDED ON REEL 60684 FRAME 822. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Mar 25, 2025
From: LIN, CHIEN-HUNG; CHEN, KO-FENG; LIN, KENG-CHU
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 070615/0532 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 1, 2022
From: LIN, CHIEN-HUNG; CHEN, KO-FENG; LIN, KENG-CHU
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 060684/0822 →
Continuity (3)
Provisional Application 63222785 · Jul 16, 2021
Provisional Application 63219956 · Jul 9, 2021
Related Publication 20230009144A1 · Jan 12, 2023
References Cited (20)
US 9093530B2 · Huang et al. · 2015 [cited by applicant]
US 9171929B2 · Lee et al. · 2015 [cited by applicant]
US 9214555B2 · Oxland et al. · 2015 [cited by applicant]
US 9236267B2 · De et al. · 2016 [cited by applicant]
US 9520482B1 · Chang et al. · 2016 [cited by applicant]
US 9548303B2 · Lee et al. · 2017 [cited by applicant]
US 9564489B2 · Yeo et al. · 2017 [cited by applicant]
US 9576814B2 · Wu et al. · 2017 [cited by applicant]
US 9601342B2 · Lee et al. · 2017 [cited by applicant]
US 9608116B2 · Ching et al. · 2017 [cited by applicant]
US 20170110577A1 · Wang · 2017 [cited by examiner]
US 20180330980A1 · Liang · 2018 [cited by examiner]
US 20200006063A1 · Chen · 2020 [cited by examiner]
US 20200006558A1 · Wu · 2020 [cited by examiner]
US 20200126987A1 · Rubin · 2020 [cited by examiner]
US 20200381537A1 · Lin · 2020 [cited by examiner]
US 20210305381A1 · Chiang · 2021 [cited by examiner]
US 20210359091A1 · Hsu · 2021 [cited by examiner]
US 20220102192A1 · Su · 2022 [cited by examiner]
US 20220293458A1 · Khaderbad · 2022 [cited by examiner]