Magneto-resistive random access memory with segmented bottom electrode
A magneto-resistive random access memory with segmented bottom electrode includes a magnetic tunnel junction pillar above a first portion of a bottom electrode layer, the first portion of the bottom electrode layer includes a metal region. A sidewall spacer is disposed along sidewalls of the magnetic tunnel junction pillar and above a second portion of the bottom electrode layer including a metal-oxide region. The first portion of the bottom electrode layer composed of the metal region and the second portion of the bottom electrode layer composed of the metal-oxide region form the segmented bottom electrode.
1. A memory device, comprising:
a magnetic tunnel junction pillar above a first portion of a segmented bottom electrode, the first portion of the segmented bottom electrode comprising a metal region; and
a sidewall spacer along sidewalls of the magnetic tunnel junction pillar, the sidewall spacer being above a second portion of the segmented bottom electrode, the second portion of the segmented bottom electrode comprising a metal-oxide region.
2. The memory device of claim 1 , further comprising:
a first conductive structure within a first dielectric layer; and
a metal cap above the first conductive structure, the metal cap being formed within a second dielectric layer located above the first dielectric layer, the segmented bottom electrode being located above the metal cap.
3. The memory device of claim 1 , further comprising:
a hardmask layer above the magnetic tunnel junction pillar.
4. The memory device of claim 1 , further comprising:
a second conductive structure above the magnetic tunnel junction pillar, the second conductive structure being located within a third dielectric layer.
5. The memory device of claim 1 , wherein the metal region of the segmented bottom electrode is below the magnetic tunnel junction pillar and comprises a single layer of a first conductive metal including at least one of Ta, TaN, Ti, TiN, Ru, RuN, RuTa, RuTaN, W, and WN.
6. The memory device of claim 5 , wherein the metal-oxide region of the segmented bottom electrode is outside the magnetic tunnel junction pillar below the sidewall spacer and comprises a single layer of a first oxide of the first conductive metal in the adjacent metal region.
7. The memory device of claim 6 , wherein the first oxide of the first conductive metal in the adjacent metal region comprises TaOx when the first conductive metal in the metal region comprises Ta.
8. The memory device of claim 1 , wherein the metal region of the segmented bottom electrode is below the magnetic tunnel junction pillar and comprises a metal/metal nitride bi-layer including a layer of a second conductive metal and a layer of a nitride of the second conductive metal above the layer of the second conductive metal.
9. The memory device of claim 8 , wherein the second conductive metal comprises at least one of Ta, Ti, Ru, and W.
10. The memory device of claim 8 , wherein the metal-oxide region of the segmented bottom electrode is outside the magnetic tunnel junction pillar below the sidewall spacer and comprises a bi-layer of oxides of the second conductive metal and the nitride of the second conductive metal in the adjacent metal region.
11. The memory device of claim 10 , wherein the bi-layer of oxides comprising the second conductive metal and the nitride of the second conductive metal in the adjacent metal region are made of TaOx and TaNOx, respectively, and the metal/metal nitride bi-layer comprising the second conductive metal and the nitride of the second conductive metal in the metal region comprises Ta and TaN, respectively.
12. The memory device of claim 1 , wherein the metal-oxide region is formed by oxidizing the second portion of the segmented bottom electrode by thermal/plasma exposure to at least one of O 2 , H 2 O and NO x .
13. A memory device, comprising:
a magnetic tunnel junction pillar above an inner region of a segmented bottom electrode, the inner region of the segmented bottom electrode comprising a metal region; and
a sidewall spacer along sidewalls of the magnetic tunnel junction pillar, the sidewall spacer being above an outer region of the segmented bottom electrode, the outer region of the segmented bottom electrode comprising a metal-oxide region.
14. The memory device of claim 13 , further comprising:
a first conductive structure within a first dielectric layer; and
a metal cap above the first conductive structure, the metal cap being formed within a second dielectric layer located above the first dielectric layer, the inner region of the segmented bottom electrode being located above the metal cap.
15. The memory device of claim 13 , further comprising:
a hardmask layer above the magnetic tunnel junction pillar.
16. The memory device of claim 13 , further comprising:
a second conductive structure above the magnetic tunnel junction pillar, the second conductive structure being located within a third dielectric layer.
17. The memory device of claim 13 , wherein the metal region is below the magnetic tunnel junction pillar and comprises a single layer of a first conductive metal including at least one of Ta, TaN, Ti, TiN, Ru, RuN, RuTa, RuTaN, W, and WN.
18. The memory device of claim 17 , wherein the metal-oxide region of the outer region comprises a single layer of a first oxide of the first conductive metal in the adjacent metal region.
19. The memory device of claim 18 , wherein the first oxide of the first conductive metal in the adjacent metal region comprises TaOx when the first conductive metal in the metal region comprises Ta.
20. The memory device of claim 13 , wherein the metal-oxide region is formed by oxidizing the outer portion of the segmented bottom electrode by thermal/plasma exposure to at least one of O 2 , H 2 O and NO x .