MRAM stack with reduced height
A memory device that includes an magnetoresistive random-access memory (MRAM) stack positioned on an electrode, a metal line in contact with the electrode, and a sidewall spacer abutting the MRAM stack. The memory device also includes a stepped reach through conductor having a first height portion of the stepped reach through conductor in an undercut region positioned between the sidewall spacer and the metal line, and a second height portion having a greater height dimensions than the first height portion abutting an outer sidewall of the sidewall spacer.
1. A memory device comprising:
a magnetic random access memory (MRAM) stack positioned on a bottom electrode;
a metal line directly in contact with the bottom electrode;
a sidewall spacer abutting the MRAM stack; and
a stepped reach through conductor having a first height portion of the stepped reach through conductor in an undercut region positioned between the sidewall spacer and the metal line, and a second height portion having a greater height dimension than the first height portion abutting an outer sidewall of the sidewall spacer on a lateral side of the sidewall spacer facing away from the MRAM stack, wherein the stepped reach through conductor connects to the metal line continuously between opposite sides of the MRAM stack and the bottom electrode.
2. The memory device of claim 1 further comprising a cap electrode contacting an opposite surface of the MRAM stack than the bottom electrode that is in contact with the metal line.
3. The memory device of claim 1 further comprising a multi-layer inner spacer portion present between the bottom electrode contacting the metal line and the sidewall spacer.
4. The memory device of claim 3 , wherein the multi-layer inner spacer portion comprises a metal cap layer present on the metal line, and a inter level dielectric layer present between the MRAM stack and the metal cap layer.
5. The memory device of claim 4 , wherein the metal cap layer has a composition selected from the group consisting of semiconductor oxide containing dielectric, a semiconductor nitride containing dielectric, a metal oxide and combinations thereof.
6. The memory device of claim 4 , wherein the metal cap layer is in contact with the first height portion of the stepped reach through conductor.
7. The memory device of claim 1 , wherein the MRAM stack is present in an MRAM portion of a substrate, and the metal line and the stepped reach through conductor extend from the MRAM portion of the substrate to a logic portion of the substrate.
8. A device comprising:
a substrate including a logic portion and a memory portion;
a memory device present in the memory portion of the substrate, the memory device including a memory stack positioned on a bottom electrode directly in contact with a memory portion of a metal line, the memory device including a sidewall spacer abutting the memory stack, wherein a stepped reach through conductor having a first height portion of the stepped reach through conductor in an undercut region positioned between the sidewall spacer and the metal line, and a second height portion with a greater height dimension than the first height portion abutting an outer sidewall of the sidewall spacer on a lateral side of the sidewall spacer, wherein the stepped reach through conductor connects to the metal line continuously between opposite sides of the memory stack and;
at least one via contact in the logic portion of the substrate, the at least one via contact is connected to an extension from the stepped reach through conductor that is present on a logic portion of the metal line that is present in the logic portion of the substrate.
9. The device of claim 8 , wherein the logic portion of the substrate includes access transistors in electrical communication with the at least one via contact.
10. The device of claim 8 further comprising a cap electrode contacting an opposite surface of the memory stack than the bottom electrode that is in contact with the metal line.
11. The device of claim 8 further comprising a multi-layer inner spacer portion present between the bottom electrode contacting the memory portion of the metal line and the sidewall spacer.
12. The device of claim 11 , wherein the multi-layer inner spacer portion comprises a metal cap layer present on the memory portion of the metal line, and a inter level dielectric layer present between the memory stack and the metal cap layer.
13. The device of claim 12 , wherein the metal cap layer has a composition selected from the group consisting of semiconductor oxide containing dielectric, a semiconductor nitride containing dielectric, a metal oxide, and combinations thereof.
14. The device of claim 13 , wherein the metal cap layer is in contact with the first height portion of the stepped reach through conductor.