AIN channel heterostructure field effect transistor
A semiconductor device having a substrate and an orthorhombic polar crystalline oxide k-Al 2 O 3 layer epitaxially and heterogeneously integrated above a wurtzite single-crystal Group III-Nitride layer comprising AlN disposed above the substrate.
1. A semiconductor device, comprising:
a polar oxide layer epitaxially and heterogeneously integrated above a wurtzite single-crystal Group III-Nitride layer comprising AlN;
a source electrode disposed over a conductive region in the polar oxide layer and partway into the AlN;
a drain electrode disposed over another conductive region in the polar oxide layer and partway into the AlN; and
a gate electrode disposed between the source electrode and the drain electrode on top of the polar oxide layer.
2. The semiconductor device recited in claim 1 , wherein the polar oxide layer comprises an alloy of orthorhombic polar oxide κ-Al 2 O 3 and κ-B 2 O 3 .
3. The semiconductor device recited in claim 1 , wherein the polar oxide layer comprises κ-B 2 O 3 .
4. The semiconductor device recited in claim 1 , wherein the polar oxide layer comprises κ-Al 2 O 3 .
5. The semiconductor device recited in claim 1 , wherein the polar oxide layer has a thickness in a range of 3 nm to 15 nm.
6. The semiconductor device recited in claim 1 , wherein the semiconductor device is a depletion mode Field Effect Transistor.
7. A semiconductor device, comprising:
a substrate;
a polar oxide layer epitaxially and heterogeneously integrated above a wurtzite single-crystal Group III-Nitride layer comprising AlN disposed above the substrate;
a source electrode disposed over a conductive region in the polar oxide layer and partway into the Group III-Nitride layer;
a drain electrode disposed over another conductive region in the polar oxide layer and partway into the Group III-Nitride layer; and
a gate electrode disposed between the source electrode and the drain electrode to provide a depletion mode Field Effect Transistor.
8. The semiconductor device recited in claim 7 , wherein the polar oxide layer has a thickness in a range of 3 nm to 15 nm.
9. The semiconductor device recited in claim 7 , wherein the source electrode and the drain electrode are in ohmic contact with the Group III-Nitride layer.
10. The semiconductor device recited in claim 7 , wherein the polar oxide layer comprises κ-Al 2 O 3 .
11. The semiconductor device recited in claim 7 , wherein the polar oxide layer comprises an alloy of κ-Al 2 O 3 and κ-B 2 O 3 .
12. The semiconductor device recited in claim 7 , wherein the polar oxide layer comprises κ-B 2 O 3 .
13. A semiconductor device, comprising:
a single crystal substrate;
an epitaxial AlN layer disposed above the substrate and forming nucleation, buffer, and channel regions of a High Electron Mobility Transistor (HEMT) structure; and
a barrier layer comprising one or more epitaxial polar oxide materials disposed above the epitaxial AlN layer.
14. The semiconductor device recited in claim 13 , wherein the single crystal substrate is one of: Si, SiC, diamond, or AlN.
15. The semiconductor device recited in claim 13 , wherein the one or more epitaxial polar oxide materials comprise κ-Al 2 O 3 .
16. The semiconductor device recited in claim 13 , wherein the one or more epitaxial polar oxide materials comprise κ-B 2 O 3 .
17. The semiconductor device recited in claim 13 , wherein the one or more epitaxial polar oxide materials comprise an alloy of κ-Al 2 O 3 and κ-B 2 O 3 .
18. The semiconductor device recited in claim 14 , wherein the barrier layer has a thickness in a range of 3 nm to 15 nm.
19. The semiconductor device recited in claim 1 , wherein the source electrode and the drain electrode are in ohmic contact with the Group III-Nitride layer.
20. The semiconductor device recited in claim 1 , further comprising a single crystal substrate including one of: Si, SiC, diamond, or AlN.