Semiconductor device including high electron mobility transistor or high hole mobility transistor and method of fabricating the same

1. A semiconductor device, comprising:

a semiconductor substrate having a vertical interface, wherein the substrate is a heterogeneous substrate;

a channel layer disposed outside the vertical interface and laterally with respect to the vertical interface, wherein the channel layer is a GaN-based material;

a channel supply layer disposed outside the channel layer; and

a buffer layer epitaxially grown from a hexagonal symmetry surface between the substrate and the channel layer, the buffer layer laterally between the vertical interface and the channel layer;

wherein at least one vertical two-dimensional carrier gas is formed in the channel layer adjacent to an interface between the channel layer and the channel supply layer;

wherein a height of the buffer layer is higher than a height of the vertical interface of the substrate in a vertical direction;

wherein the channel layer includes a first polar face at a portion of the interface between the channel layer and the channel supply layer, wherein a vertical two-dimensional electron gas 2DEG is formed in the channel layer, and the 2DEG is adjacent to the first polar face.

2. The semiconductor device according to claim 1 , wherein the vertical interface includes a crystalline lattice of a hexagonal symmetry.

3. The semiconductor device according to claim 1 , wherein the substrate is a Si substrate, and the vertical interface is a (111) plane of Si.

4. The semiconductor device according to claim 1 , wherein the substrate is an Al 2 O 3 sapphire substrate, and the vertical interface is a (0001) plane of Al 2 O 3 .

5. The semiconductor device according to claim 1 , wherein the substrate is a SiC substrate, and the vertical interface is a (0001) plane or a (000-1) plane of SiC.

6. The semiconductor device according to claim 1 , wherein the channel layer includes a second polar face at a portion of the interface between the channel layer and the channel supply layer, wherein a vertical two- dimensional hole gas 2DHG is formed in the channel layer, and the 2DHG is adjacent to the second polar face.

7. The semiconductor device according to claim 6 , wherein one or more electrodes are formed outside of the channel supply layer adjacent to the 2DHG region.

8. The semiconductor device according to claim 1 , wherein the channel layer includes a first polar face at a first portion of the interface between the channel layer and the channel supply layer and a second polar face at a second portion of the interface between the channel layer and the channel supply layer, wherein a 2DEG is in the channel layer and adjacent to the first polar face, and a 2DHG is in the channel layer and adjacent to the second polar face.

9. The semiconductor device according to claim 1 , further comprising a nucleation layer on the vertical interface of the substrate.

10. The semiconductor device according to claim 1 , further comprising a nucleation layer, wherein the nucleation layer is located on the vertical interface of the substrate.

11. The semiconductor device according to claim 1 , wherein a height of the channel layer is higher than a height of the substrate in a vertical direction.

12. The semiconductor device according to claim 1 , wherein one or more electrodes are formed outside of the channel supply layer adjacent to the 2DEG region.

13. The semiconductor device according to claim 1 , further comprising a insulating layer is located between the substrate and the channel layer as well as between the substrate and the channel supply layer.

14. A method of fabricating a semiconductor device, comprising the steps of:

forming a vertical interface on a substrate, wherein the substrate is a heterogeneous substrate;

forming a buffer layer from a hexagonal symmetry surface outside the vertical interface, wherein a height of the buffer layer is higher than a height of the vertical interface of the substrate in a vertical direction;

forming a semiconductor channel layer outside the vertical interface, wherein the semiconductor channel layer includes at least one of a (0001) polar face or a (000-1) polar face of a III-V compound semiconductor; and

forming a semiconductor channel supply layer outside the channel layer;

wherein a vertical two-dimensional carrier gas is formed in the semiconductor channel layer adjacent to an interface between the semiconductor channel layer and the semiconductor channel supply layer.

15. The method according to claim 14 , further comprising forming insulating layers on the substrate.

16. The method according to claim 14 , further comprising forming a nucleation layer on the vertical interface.

17. A semiconductor device, comprising:

a column having a sidewall surface; and

one or more electrodes disposed on the side wall surface of the column;

a semiconductor substrate having a vertical interface, wherein the column is formed overlaying the vertical interface of the semiconductor substrate;

wherein the column includes a buffer layer and a channel layer over the buffer layer, the buffer layer epitaxially grown from a hexagonal symmetry surface between the semiconductor substrate and the channel layer;

wherein a height of the buffer layer is higher than a height of the vertical interface of the semiconductor substrate in a vertical direction;

wherein the channel layer of the column includes at least one of a two-dimensional electron gas (2DEG) region and a two-dimensional hole gas (2DHG) region adjacent to the sidewall surface;

wherein the sidewall surface of the column includes at least one of a (0001) polar face or a (000-1) polar face of a III-V compound semiconductor.

18. The semiconductor device according to claim 17 , wherein the column includes a first sidewall surface and a second sidewall surface, wherein the 2DEG is adjacent to the first sidewall surface and the 2DHG is adjacent to the second sidewall surface.

19. The semiconductor device according to claim 17 , wherein the column comprises:

a channel layer; and

a channel supply layer at least partially overlaying a sidewall surface of the channel layer.

20. A semiconductor device, comprising:

a semiconductor substrate having a vertical interface, wherein the substrate is a heterogeneous substrate;

a channel layer disposed outside the vertical interface and laterally with respect to the vertical interface, wherein the channel layer is a GaN-based material;

a channel supply layer disposed outside the channel layer; and

a buffer layer epitaxially growing from a hexagonal symmetry surface between the substrate and the channel layer, the buffer layer laterally between the vertical interface and the channel layer;

wherein at least one vertical two-dimensional carrier gas is formed in the channel layer adjacent to an interface between the channel layer and the channel supply layer;

wherein a height of the buffer layer is higher than a height of the vertical interface of the substrate in a vertical direction;

wherein the channel layer includes a second polar face at a portion of the interface between the channel layer and the channel supply layer, wherein a vertical two-dimensional hole gas 2DHG is formed in the channel layer, and the 2DHG is adjacent to the second polar face.

21. A semiconductor device, comprising:

a semiconductor substrate having a vertical interface, wherein the substrate is a heterogeneous substrate;

a channel layer disposed outside the vertical interface and laterally with respect to the vertical interface, wherein the channel layer is a GaN-based material;

a channel supply layer disposed outside the channel layer; and

a buffer layer epitaxially growing from a hexagonal symmetry surface between the substrate and the channel layer, the buffer layer laterally between the vertical interface and the channel layer;

wherein at least one vertical two-dimensional carrier gas is formed in the channel layer adjacent to an interface between the channel layer and the channel supply layer;

wherein a height of the buffer layer is higher than a height of the vertical interface of the substrate in a vertical direction;

wherein the channel layer includes a first polar face at a first portion of the interface between the channel layer and the channel supply layer and a second polar face at a second portion of the interface between the channel layer and the channel supply layer, wherein a 2DEG is in the channel layer and adjacent to the first polar face, and a 2DHG is in the channel layer and adjacent to the second polar face.