High electron mobility transistor (HEMT) and method of manufacturing the same
The present disclosure relates to a HEMT, which comprises a vertical interface; a channel layer disposed outside of the vertical interface; a channel supply layer disposed outside of the channel layer, wherein a vertical 2 DEG is formed in the channel layer adjacent to an interface between the channel layer and the channel supply layer; a first electrode configured to be electrically connected to the vertical 2 DEG; a second electrode configured to be electrically connected to the vertical 2 DEG; a gate electrode disposed outside of the channel supply layer. The present disclosure also relates to a method of manufacturing a HEMT, which comprises forming a vertical interface; forming a channel layer outside of the vertical interface; forming a channel supply layer outside the channel layer, wherein a vertical 2 DEG is formed in the channel layer adjacent to an interface between the channel layer and the channel supply layer; and forming a first electrode and a second electrode which are electrically connected to the 2 DEG, and a gate electrode which form schottky contact to the 2 DEG.
1 . A high electron mobility transistor (HEMT), comprising:
a vertical interface which is substantially perpendicular to a substrate surface;
a channel layer disposed outside of the vertical interface;
a channel supply layer disposed outside of the channel layer, wherein a vertical two-dimensional electron gas (2DEG) is formed in the channel layer adjacent to an interface between the channel layer and the channel supply layer;
a first electrode configured to be electrically connected to the vertical two-dimensional electron gas (2DEG);
a second electrode configured to be electrically connected to the vertical two-dimensional electron gas (2DEG); and
a gate electrode disposed outside the channel supply layer;
wherein the vertical interface is a (111) plane of Si, a (0001) plane of Al 2 O 3 , a (0001) plane or a (000-1) plane of SiC, or a (0001) plane of GaN intrinsic substrate;
wherein the substrate includes a first area and a second area, the first area is higher than the second area, the vertical two-dimensional electron gas (2DEG) is formed above the second area, and the vertical two-dimensional electron gas (2DEG) has a larger height than the vertical interface.
2 . The high electron mobility transistor according to claim 1 , wherein the first electrode or the second electrode form an ohmic contact with the channel supply layer.
3 . The high electron mobility transistor according to claim 1 , wherein the first electrode, the second electrode, and the gate electrode are at a same side of the two-dimensional electron gas (2DEG).
4 . The high electron mobility transistor according to claim 3 , wherein the first electrode, the second electrode, and the gate electrode are in a same level or in a same upright position.
5 . The high electron mobility transistor according to claim 1 , wherein the first electrode and the second electrode are at a different side of the two-dimensional electron gas (2DEG) with the gate electrode.
6 . The high electron mobility transistor according to claim 1 , wherein the first electrode extends under the channel layer.
7 . The high electron mobility transistor according to claim 6 , wherein the first electrode is a drain electrode.
8 . The high electron mobility transistor according to claim 1 , wherein the second electrode extends on the channel layer.
9 . The high electron mobility transistor according to claim 8 , wherein the second electrode is a source electrode.
10 . The high electron mobility transistor according to claim 1 , further comprising a nucleation layer on the vertical interface of the substrate.
11 . The high electron mobility transistor according to claim 10 , further comprising a buffer layer located between the nucleation layer and the channel layer.
12 . The high electron mobility transistor according to claim 1 , further comprising a shielding layer formed on a side of the channel layer nonadjacent to the two-dimensional electron gas (2DEG).
13 . The high electron mobility transistor according to claim 1 , further comprising an insulating layer extending under the channel layer and the channel supply layer.
14 . The high electron mobility transistor according to claim 1 , further comprising a gate insulating layer between the channel supply layer and the gate electrode.
15 . A high electron mobility transistor (HEMT), comprising:
a column including a channel layer and a channel supply layer which vertically extend on at least one side of the column, wherein a vertical two-dimensional electron gas (2DEG) is formed in the channel layer adjacent to an interface between the channel layer and the channel supply layer;
a first electrode contacted with the column and being electrically connected with the vertical two-dimensional electron gas (2DEG);
a second electrode contacted with the column and being electrically connected with the vertical two-dimensional electron gas (2DEG); and
a third electrode, disposed on the column;
wherein the vertical two-dimensional electron gas (2DEG) is perpendicular to a substrate surface;
wherein the substrate includes a first area, a second area, and a vertical interface between the first area and the second area, the first area higher than the second area,
wherein the vertical two-dimensional electron gas (2DEG) is formed above the second area, and the vertical two-dimensional electron gas (2DEG) has a larger height than the vertical interface, and
wherein the vertical in is a (111) plane of Si, a (0001) plane of Al 2 O 3 , a (0001) plane or a (000-1) plane of SiC, or a (0001) plane of GaN intrinsic substrate.
16 . The high electron mobility transistor according to claim 15 , the first electrode or the second electrode is a source electrode or a drain electrode.
17 . The high electron mobility transistor according to claim 15 , further comprising a gate insulating layer between the channel supply layer and the third electrode.
18 . The high electron mobility transistor according to claim 15 , wherein the first electrode, the second electrode and the third electrode are on the side of the column.
19 . The high electron mobility transistor according to claim 15 , wherein the first electrode is on a top of the column.
20 . The high electron mobility transistor according to claim 15 , wherein the second electrode is on a bottom of the column.
21 . The high electron mobility transistor according to claim 19 , wherein an area of the second electrode is larger than a base area of the column.
22 . A method of manufacturing a high electron mobility transistor (HEMT), comprising:
forming a vertical interface which is perpendicular to a substrate surface;
forming a channel layer outside of the vertical interface; and
forming a channel supply layer outside of the channel layer, wherein a vertical two-dimensional electron gas (2DEG) is formed in the channel layer adjacent to an interface between a semiconductor channel layer and the channel supply layer; and
forming a first electrode and a second electrode electrically connected to the two-dimensional electron gas (2DEG), and a gate electrode outside of the channel supply layer;
wherein the vertical interface is a (111) plane of Si, a (0001) plane of Al 2 O 3 , a (0001) plane or a (000-1) plane of SiC, or a (0001) plane of GaN intrinsic substrate;
wherein the substrate includes a first area and a second area, the first area is higher than the second area, the vertical two-dimensional electron gas (2DEG) is formed above the second area and the vertical two-dimensional electron gas (2DEG) has a larger height than the vertical interface.
23 . The method according to claim 22 , wherein the vertical interface is formed on the substrate.
24 . The method according to claim 22 , further comprising forming a gate insulating layer between a channel supply layer and the gate electrode.
25 . The method according to claim 22 further comprising, before forming the first electrode and the second electrode electrically connected to the two-dimensional electron gas (2DEG), transversely etching the channel supply layer or the channel supply layer and a part of the channel layer.
26 . The method according to claim 22 , further comprising forming a nucleation layer on the vertical interface, wherein Chlorine gas is aerated while forming a nucleation layer.
27 . The method according to claim 22 , further comprising,
forming the second electrode and gate electrode electrically connected to the two-dimensional electron gas (2DEG);
etching the substrate or a part of the substrate; and
forming the first electrode under the channel layer and the channel supply layer.