IP Library › Granted Patent US 12,512,426
Granted Patent B2
US 12,512,426 · App. 17/656,104 · Granted Dec 30, 2025

Package structure and method for forming same

Inventor: Ling-Yi Chuang (Hefei, CN)
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
H01L24/08H01L24/03H01L24/04H01L24/05H01L24/06H01L24/09H01L24/16H01L24/80H01L25/105H01L24/13H01L2224/0345H01L2224/03452H01L2224/03614H01L2224/05541H01L2224/05557H01L2224/05688H01L2224/0603H01L2224/06051H01L2224/06505H01L2224/08148H01L2224/09505H01L2224/13147H01L2224/16146H01L2224/80097H01L2224/80895H01L2224/80896H01L2224/80948H01L2225/1058H01L2924/1431H01L2924/1436
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Quick Facts
Patent No.
US 12,512,426
App. No.
17/656,104
Granted
Dec 30, 2025
Kind
B2
Abstract

A package structure includes the following: a logic die; and a plurality of core dies sequentially stacked on the logic die along a vertical direction, in which the plurality of core dies include a first core die and a second core die interconnected through a hybrid bonding member; the hybrid bonding member includes: a first contact pad located on a surface of the first core die; and a second contact pad located on a surface of the second core die; the first contact pad is in contact bonding with the second contact pad.

Claims (17)

1 . A method for forming a package structure, comprising:

providing a logic die, a first core die and a second core die;

respectively arranging a first contact pad and a second contact pad on a surface of the first core die and a surface of the second core die, a first dielectric layer located on a periphery of the first contact pad, and a second dielectric layer located on a periphery of the second contact pad, which further comprises:

respectively forming the first dielectric layer and the second dielectric layer on the first core die and the second core die;

etching the first dielectric layer and the second dielectric layer to respectively form a first via and a second via; and

respectively forming the first contact pad and the second contact pad in the first via and the second via, wherein a top surface of the first contact pad is higher than a surface of the first dielectric layer, and a top surface of the second contact pad is lower than a surface of the second dielectric layer;

sequentially stacking the first core die and the second core die on the logic die, to allow the first contact pad and the second contact pad butted; and

performing a bonding process, to form a hybrid bonding member by allowing the first contact pad and the second contact pad to bond to each other, and the first dielectric layer and the second dielectric layer to bond to each other.

2 . The method of claim 1 , wherein after the first contact pad and the second contact pad are respectively formed in the first via and the second via, the method further comprises:

etching the first contact pad to form a gap area between a side wall of the first contact pad and a side wall of the first via; and/or

etching the second contact pad to from a gap area between a side wall of the second contact pad and a side wall of the second via.

3 . The method of claim 2 , wherein after the gap area is formed, the method further comprises:

depositing an insulating material, wherein the insulating material is filled in the gap area; a Young's modulus of the insulating material is less than Young's moduli of the first dielectric layer and the second dielectric layer.

4 . The method of claim 1 , wherein

a bonding temperature of the bonding process is less than 200 degrees Celsius.

5 . The method of claim 1 , wherein

the bonding process adopts an annealing process being performed alternately at two temperatures.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 23, 2022
From: CHUANG, LING-YI
To: CHANGXIN MEMORY TECHNOLOGIES, INC.
Reel/Frame 059377/0320 →
Priority Claims (1)
CN 202210066315.0 · Jan 20, 2022 · national
Continuity (1)
Related Publication 20230230945A1 · Jul 20, 2023
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