IP Library Granted Patent US 12,294,024
Granted Patent B2
US 12,294,024 · App. 17/660,729 · Granted May 6, 2025

Method of manufacturing semiconductor device

Inventors: Hajime Watakabe (Tokyo, JP); Masashi Tsubuku (Tokyo, JP); Kentaro Miura (Tokyo, JP); Akihiro Hanada (Tokyo, JP); Takaya Tamaru (Tokyo, JP)
Assignee: Japan Display Inc.
H01L29/66969H01L21/426H01L21/47573H01L21/47635H01L29/401H01L29/78621H01L29/42384H01L29/7869
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Quick Facts
Patent No.
US 12,294,024
App. No.
17/660,729
Granted
May 6, 2025
Kind
B2
Abstract

According to one embodiment, a method of manufacturing a semiconductor device, includes forming a first insulating layer, an oxide semiconductor layer, a second insulating layer, a buffer layer and a metal layer sequentially on a base, forming a patterned resist on the metal layer, etching the buffer layer and the metal layer using the resist as a mask to expose an upper surface of the second insulating layer, reducing a volume of the resist to expose an upper surface along a side surface of the metal layer, etching the metal layer using the resist as a mask, to form a gate electrode and to expose an upper surface of the buffer layer, and carrying out ion implantation on the oxide semiconductor layer using the gate electrode as a mask.

Claims (13)

1. A method of manufacturing a semiconductor device, comprising:

forming a first insulating layer, an oxide semiconductor layer, a second insulating layer, a buffer layer and a metal layer sequentially on a base;

forming a patterned resist on the metal layer;

etching the buffer layer and the metal layer using the resist as a mask to expose an upper surface of the second insulating layer;

reducing a volume of the resist to expose an upper surface along a side surface of the metal layer;

etching the metal layer using the resist as a mask, to form a gate electrode including a first side surface and to expose an upper surface along a second side surface of the buffer layer; and

carrying out ion implantation on the oxide semiconductor layer using the gate electrode as a mask.

2. The manufacturing method of claim 1 , wherein

the buffer layer is a silicon oxide layer.

3. The manufacturing method of claim 1 , wherein

the buffer layer is an oxide semiconductor layer.

4. The manufacturing method of claim 1 , wherein

a width from the first side surface to the second side surface is 0.5 μm or greater.

Assignments (2)
CHANGE OF NAME Recorded Aug 27, 2025
From: JAPAN DISPLAY INC.
To: MAGNOLIA WHITE CORPORATION
Reel/Frame 073057/0042 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 26, 2022
From: WATAKABE, HAJIME; TSUBUKU, MASASHI; MIURA, KENTARO; HANADA, AKIHIRO; TAMARU, TAKAYA
To: JAPAN DISPLAY INC.
Reel/Frame 059734/0102 →
Priority Claims (1)
JP 2021-080436 · May 11, 2021 · national
Continuity (1)
Related Publication 20220367691A1 · Nov 17, 2022
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