Granted Patent B2

US 12,451,431 · App. 17/661,583 · Granted Oct 21, 2025

Inventors: Tao Li (Slingerlands, NY); Liqiao Qin (Albany, NY); Mukta Ghate Farooq (Hopewell Jct, NY); Ruilong Xie (Niskayuna, NY); Kisik Choi (Watervliet, NY)

Assignee: International Business Machines Corporation

H01L23/5286H01L23/481H01L24/33H01L24/48H01L25/0657H01L2224/04042H01L2224/48227H01L2224/73265H01L2225/06541

Abstract

Claims (40)

1. A semiconductor structure comprising:

a first semiconductor device on a substrate;

a first interconnect wiring structure over the first semiconductor device;

a second interconnect wiring structure under a second semiconductor device, wherein the second interconnect wiring structure physically contacts the first interconnect wiring structure;

a third interconnect wiring structure (i) on the second semiconductor device and (ii) electrically contacting the second semiconductor device through a top surface of the second semiconductor device; and

a first through-silicon via from a bottom surface of the substrate to a top surface of the first interconnect wiring structure, wherein the first through-silicon via is tapered such that a width of a bottom surface of the first through-silicon via is greater than a width of a top surface of the first through-silicon via.

2. The semiconductor structure of claim 1 , wherein the first semiconductor device and the second semiconductor device are each selected from the group consisting of: a memory device and a logic device.

3. The semiconductor structure of claim 1 , wherein the first interconnect wiring structure, the second interconnect wiring structure, and the third interconnect wiring structure each has a contact pitch on a bottom surface that is less than one hundred nanometers.

4. The semiconductor structure of claim 3 , wherein:

the second interconnect wiring structure is a frontside interconnect wiring structure for the second semiconductor device; and

the third interconnect wiring structure is a backside interconnect wiring structure, for the second semiconductor device, providing a backside power delivery network.

5. The semiconductor structure of claim 1 , further comprising:

a second through-silicon via connecting from the first through-silicon via to a top surface of the third interconnect wiring structure, wherein the first through-silicon via and the second through-silicon via are centered along a single axis.

6. A semiconductor structure comprising:

a first semiconductor device on a substrate;

a first interconnect wiring structure over the first semiconductor device;

a second interconnect wiring structure under a second semiconductor device, wherein the second interconnect wiring structure contacts the first interconnect wiring structure;

a third interconnect wiring structure on the second semiconductor device, wherein:

the third interconnect wiring structure contacts a fourth interconnect wiring structure; and

the fourth interconnect wiring structure is under a third semiconductor device;

a fifth interconnect wiring structure on the third semiconductor device;

a first through-silicon via from a bottom surface of the substrate to a top surface of the first interconnect wiring structure, wherein the first through-silicon via is tapered such that a width of a bottom surface of the first through-silicon via is greater than a width of a top surface of the first through-silicon via; and

a second through-silicon via connecting from the first through-silicon via to a top surface of the third interconnect wiring structure, wherein the second through-silicon via is tapered opposite that of the first through-silicon via.

7. The semiconductor structure of claim 6 , wherein the first through-silicon via and the second through-silicon via are centered along a single axis, further comprising:

a third through-silicon via connecting from a top surface of the third interconnect wiring structure to a top surface of the fifth interconnect wiring structure.

8. The semiconductor structure of claim 6 , wherein the first semiconductor device, the second semiconductor device, and the third semiconductor device are each selected from a group consisting of: a logic device and a memory device.

9. The semiconductor structure of claim 6 , wherein the third interconnect wiring structure has a contact pitch of less than one hundred nanometers with the second semiconductor device.

10. The semiconductor structure of claim 6 , wherein the second semiconductor device and the third semiconductor device each have both a frontside interconnect wiring structure and a backside interconnect wiring structure.

11. The semiconductor structure of claim 6 , further comprising:

a sixth interconnect wiring structure under a fourth semiconductor device connected to the fifth interconnect wiring structure; and

a seventh interconnect wiring structure on the fourth semiconductor device, wherein at least a fourth through-silicon via connects from a top surface of the seventh interconnect wiring structure to a top surface of the sixth interconnect wiring structure.

12. The semiconductor structure of claim 6 , wherein the second interconnect wiring structure under the second semiconductor device joined to the first interconnect wiring structure is joined by a plurality of wiring pads on a top surface of the first interconnect wiring structure bonded by thermal compression bonding to the plurality of wiring pads on a top surface of the second interconnect wiring structure.

13. The semiconductor structure of claim 6 , further comprising:

a first through-silicon via from a bottom surface of the substrate to a top surface of the first interconnect wiring structure;

a second through-silicon via connecting from the first through-silicon via to a top surface of the third interconnect wiring structure; and

a third through-silicon via connecting from a top surface of the third interconnect wiring structure to a top surface of the fifth interconnect wiring structure, wherein the second semiconductor device and the third semiconductor device each have a backside interconnect wiring structure and a frontside interconnect wiring structure.

14. The semiconductor structure of claim 13 , wherein the first through-silicon via connects to the second through-silicon via and the third through-silicon via connects to the second through-silicon via.

15. The semiconductor structure of claim 14 , wherein:

the first through-silicon via connects to the second through-silicon via and the third through-silicon via connects to the second through-silicon via, and

the first through-silicon via connects from a bottom surface of the substrate through the second through-silicon via and through the third through-silicon via to a top surface of the fifth interconnect wiring structure.

Assignments (1)

Continuity (1)

References Cited (29)