Semiconductor device including nonvolatile memory device and logic device and manufacturing method of semiconductor device including nonvolatile memory device and logic device

1. A manufacturing method of a semiconductor device, the manufacturing method comprising:

forming a nonvolatile memory device, comprising:

forming a first well region in a substrate,

forming a tunneling gate insulator on the first well region,

forming a floating gate on the tunneling gate insulator,

forming a thick dielectric pattern formed on sidewalls of the floating gate,

forming a control gate insulator on the substrate,

forming a control gate on the control gate insulator, and

forming a first source region and a first drain region on opposite sides of the control gate, respectively; and

forming a first logic device, comprising:

forming a first logic gate insulator on the substrate,

forming a first logic gate on the first logic gate insulator, wherein the first logic gate and the control gate are formed in the same operation,

forming a first logic well region by performing a first ion implantation of dopants passing through the first logic gate into the substrate,

forming first logic gate spacers formed on sidewalls of the first logic gate, and

forming a first logic source region and a first logic drain region on opposite sides of the first logic gate, respectively,

wherein the first logic well region has a depth shallower below the first logic gate than a depth of the first logic well region with respect to the first logic source region and the first logic drain region, and

wherein the forming of the first logic gate comprises simultaneously forming the control date and the first logic gate, using a hard mask pattern to form the first logic gate and not using the hard mask pattern to form the control gate.

2. The method of claim 1 , wherein the forming a nonvolatile memory device further comprises:

forming control gate spacers on sidewalls of the control gate; and

forming a first silicide layer on the control gate.

3. The method of claim 1 , wherein the forming a nonvolatile memory device further comprises:

forming a deep well region in the substrate, wherein the deep well region has a depth greater than a depth of the first well region and greater than a depth of the first logic well region; and

forming a lightly-doped drain (LDD) region in the first well region, wherein the LDD region has a depth greater than a depth of the first source region and greater than a depth of the first drain region.

4. The method of claim 1 , wherein the forming of a floating gate on the tunneling gate insulator comprises:

forming a first conductive film on the tunneling gate insulator;

forming a first hard mask pattern on the first conductive film; and

performing an etching of the first conductive film using the first hard mask pattern as a mask, thereby forming the floating gate on the tunneling gate insulator,

wherein the first hard mask pattern remains on a top surface of the floating gate.

5. The method of claim 1 , wherein the forming a control gate on the control gate insulator comprises:

depositing a second conductive film on the control gate insulator and the floating gate; and

patterning the second conductive film using an etch-back process, thereby forming the control gate on the control gate insulator and on sidewalls of the thick dielectric pattern,

wherein no control gate is formed on a top surface of the floating gate.

6. The method of claim 5 , wherein the forming a control gate on the control gate insulator further comprises:

depositing a stacked layer on the second conductive film;

patterning the stacked layer, thereby forming a stacked layer pattern on sidewalls of the second conductive film;

removing the stacked layer pattern by wet etching using chemical etchants; and

implanting dopants into the second conductive film.

7. The method of claim 1 , wherein the forming of the first logic gate on the first logic gate insulator comprises:

forming the first logic gate insulator on the substrate;

forming a second conductive film on the first logic gate insulator;

forming the hard mask pattern on the second conductive film; and

patterning the second conductive film, using the hard mask pattern, to form the first logic gate on the first logic gate insulator.

8. The method of claim 1 , wherein the control gate is formed to enclose the floating gate.

9. A manufacturing method of a semiconductor device, the manufacturing method comprising:

preparing a substrate comprising a cell region and a logic region, wherein a nonvolatile memory device is formed on the cell region and a logic device is formed on the logic region;

forming a first well region in the cell region of the substrate;

forming a tunneling gate insulator on the first well region;

forming a first conductive film on the tunneling gate insulator;

patterning the first conductive film, thereby forming a floating gate on the tunneling gate insulator;

forming a thick dielectric pattern on sidewalls of the floating gate;

forming a control gate insulator on the cell region;

forming a first logic gate insulator on the logic region;

forming a second conductive film on the logic gate insulator and the control gate insulator;

patterning the second conductive film, thereby forming a control gate on the control gate insulator and forming a first logic gate on the first logic gate insulator, such that the first logic gate and the control gate are formed in the same operation;

forming a first logic well region by performing a first ion implantation of dopants that pass through the first logic gate into the substrate;

forming control gate spacers formed on each sidewall of the control gate and first logic gate spacers on each sidewall of the first logic gate;

forming a first source region and a first drain region on opposite sides of the control gate, respectively; and

forming a first logic source region and a first logic drain region on opposite sides of the first logic gate, respectively,

wherein the first logic well region has a depth shallower below the first logic gate than a depth of the first logic well region with respect to the first logic source region and the first logic drain region, and

wherein the forming of the control gate and the first logic gate comprises simultaneously forming the control gate and the first logic gate, using a hard mask pattern to form the first logic gate and not using the hard mask pattern to form the control gate.

10. The method of claim 9 , wherein the patterning the first conductive film comprises:

forming a first hard mask pattern on the first conductive film; and

performing an etching of the first conductive film using the first hard mask pattern as a mask, thereby forming the floating gate on the tunneling gate insulator, wherein the first hard mask pattern remains on a top surface of the floating gate.

11. The method of claim 9 , wherein the patterning the second conductive film comprises:

forming the hard mask pattern on the second conductive film on the logic region, wherein no hard mask pattern is formed on the second conductive film on the cell region; and

performing an etching process on the second conductive film using the hard mask pattern as a mask, such that the first logic gate and the control gate are simultaneously formed on the logic region and the cell region, respectively.

12. The method of claim 9 , further comprising:

forming a deep well region formed in the substrate, wherein the deep well region encloses the first well region; and

forming an LDD region formed in the first well region, wherein the LDD region encloses the first source region and the first drain region.

13. The method of claim 9 , further comprising:

forming a second logic well region by performing a second ion implantation of dopants passing through the second logic gate into the substrate;

forming a second logic source region and a second logic drain region on opposite sides of the second logic gate, respectively; and

wherein the second logic well region has a depth shallower below the second logic gate than a depth of the second logic well region with respect to the second logic source region and the second logic drain region.