Semiconductor devices with crystallized channel regions and methods of manufacturing thereof
Example implementations can include a semiconductor device with a first seed layer including a first material and having a planar structure, the first material having a two-dimensional structure, a first device layer including a second material and disposed over a first surface of the first seed layer, the second material having a crystallized structure, and a second device layer including the second material and disposed over a second surface of the first seed layer opposite to the first surface of the first seed layer.
1. A semiconductor device, comprising:
a first metal contact;
a second metal contact;
a seed layer extending from the first metal contact to the second metal contact;
a first terminal layer coupled between a first end of the seed layer and the first metal contact;
a second terminal layer coupled between a second end of the seed layer and the second metal contact;
a re-crystallized two-dimensional (2D) material wrapping around the seed layer, a portion of the first terminal layer, and a portion of the second terminal layer; and
a gate structure wrapping around the re-crystallized 2D material.
2. The device of claim 1 , wherein
the first terminal layer includes a first terminal material and has a planar structure; and
the second terminal layer includes the first terminal material and has the planar structure.
3. A CFET semiconductor device comprising:
a first seed layer including a first material having a planar structure, the first material having a two-dimensional structure and one of a PMOS or NMOS property;
a first terminal layer and a second terminal layer in contact with ends of the first seed layer, respectively;
a first re-crystallized material wrapping around the first seed layer, a portion of the first terminal layer, and a portion of the second terminal layer;
a second seed layer including a second material having the planar structure, the first second material having the two-dimensional structure and one of a PMOS or NMOS property different from the PMOS or NMOS property of the first seed layer;
a third terminal layer and a fourth terminal layer in contact with ends of the second seed layer, respectively; and
a second re-crystallized material wrapping around the second seed layer, a portion of the third terminal layer, and a portion of the fourth terminal layer.
4. The device of claim 3 , wherein the first re-crystallized material is an NMOS material and the second re-crystallized material is a PMOS material.
5. The device of claim 3 , further comprising:
a first metal and a second metal coupled to ends of the first seed layer through the first terminal layer and the second terminal layer, respectively; and
a third metal and a fourth metal coupled to ends of the second seed layer through the third terminal layer and the fourth terminal layer, respectively.
6. The device of claim 5 , further comprising:
a third seed layer including the first material and having the planar structure;
a third re-crystallized material around the third seed layer;
a fourth seed layer including a second material and having the planar structure; and
a fourth re-crystallized material around the fourth seed layer.
7. The device of claim 6 , wherein the first metal and the second metal are coupled to the third seed layer, and the third metal and the fourth metal are coupled to the fourth seed layer.
8. The device of claim 7 , wherein the first seed layer and the third seed layer comprise a PMOS material.
9. The device of claim 7 , wherein the second seed layer and the fourth seed layer comprise an NMOS material.
10. A semiconductor device, comprising:
a first metal contact;
a first terminal layer in contact with the first metal contact and including a terminal material;
a second terminal layer disposed above the first terminal layer, in contact with the first metal contact, and including the terminal material;
a second metal contact;
a third terminal layer in contact with the second metal contact and including the terminal material;
a fourth terminal layer disposed above the third terminal layer, in contact with the second metal contact, and including the terminal material;
a first seed layer extending from the first terminal layer to the second terminal layer;
a first re-crystallized two-dimensional (2D) material wrapping around the first seed layer, a portion of the first terminal layer, and a portion of the second terminal layer;
a first gate structure wrapping around the first re-crystallized 2D material;
a second seed layer extending from the third terminal layer to the fourth terminal layer;
a second re-crystallized 2D material wrapping around the second seed layer, a portion of the third terminal layer, and a portion of the fourth terminal layer; and
a second gate structure wrapping around the second re-crystallized 2D material.
11. The device of claim 10 , wherein the first seed layer has one of a PMOS or NMOS property.
12. The device of claim 11 , wherein the second seed layer has one of a PMOS or NMOS property different from the PMOS or NMOS property of the first seed layer.