Encapsulation for transition metal dichalcogenide nanosheet transistor and methods of fabrication
A transistor includes a channel layer including a transition metal dichalcogenide (TMD) material, an encapsulation layer on a first portion of the channel layer, a gate electrode above the encapsulation layer, a gate dielectric layer between the gate electrode and the encapsulation layer. The transistor further includes a source contact on a second portion of the channel layer and a drain contact on a third portion of the channel layer, where the gate structure is between drain contact and the source contact.
1. An apparatus, comprising:
a first transistor of a first conductivity type, the first transistor comprising:
a first channel region comprising a transition metal and a chalcogen;
a first gate electrode coupled to the first channel region;
an encapsulation material in direct contact with the first channel region, wherein the encapsulation material comprises oxygen and a second metal, different than the transition metal;
a first gate insulator between the first gate electrode and the encapsulation material, wherein the first gate insulator is in direct contact with the encapsulation material; and
a first source contact and a first drain contact coupled to the first channel region, wherein the first gate electrode and the encapsulation material are between the first drain contact and the first source contact;
a second transistor of a complementary second conductivity type and laterally adjacent to the first transistor, the second transistor comprising:
a second channel region comprising the transition metal and the chalcogen, but not in direct contact with the encapsulation material;
a second gate electrode coupled to the second channel region;
a second gate insulator between the second gate electrode and the second channel region; and
a second source contact and a second drain contact coupled to the second channel region, wherein the second gate electrode is between the second drain contact and the second source contact.
2. The apparatus of claim 1 , wherein the first conductivity type is n-type and the second conductivity type is p-type.
3. The apparatus of claim 1 , wherein:
the first channel region is over a third channel region, wherein the first and the third channel regions each comprise the transition metal and the chalcogen; and
the encapsulation layer is in direct contact with the first channel region and in direct contact with the third channel region.
4. The apparatus of claim 3 , wherein the transition metal comprises molybdenum, tungsten or chromium, wherein the chalcogen comprises sulfur, selenium or tellurium and wherein the first and third channel regions each have a thickness between 1 and 4 monolayers.
5. The apparatus of claim 3 , wherein the second metal comprises aluminum, tungsten, or molybdenum, and the encapsulation layer has a thickness between 0.5 nm and 3 nm.
6. The apparatus of claim 3 , wherein each of the first and third channel regions has a first thickness along a first direction orthogonal to a length of the first and second channel regions, wherein each of the first and second channel regions have a second thickness along a second direction orthogonal to the first direction and orthogonal to the length, wherein the first thickness is between 5 nm and 60 nm, and wherein the second thickness is between 1 and 4 monolayers, and wherein the encapsulation layer clads each of the first and the second channel regions in the first and in the second directions.
7. The apparatus of claim 1 , wherein:
the second metal is aluminum;
the second transistor comprises a second encapsulation material in direct contact with the second channel region and in direct contact with the second gate insulator; and
the second encapsulation material comprises oxygen and molybdenum or tungsten.
8. The apparatus of claim 1 , wherein
the gate insulator comprises a third metal, different from the second metal.
9. The apparatus of claim 1 , wherein the transition metal comprises at least one of molybdenum, tungsten, titanium or chromium, and the chalcogen comprises sulfur, selenium or tellurium.
10. The apparatus of claim 1 , wherein the first channel region has a thickness between 1 and 4 monolayers.
11. The apparatus of claim 1 , wherein the encapsulation layer comprises a sub-stoichiometric aluminum oxide, tungsten oxide, or molybdenum oxide.
12. The apparatus of claim 1 , wherein the first gate insulator and the second gate insulator comprise a same material.
13. The apparatus of claim 1 , wherein the second gate insulator is in direct contact with the second channel region.