Isolation structure for semiconductor device
A device includes a first semiconductor structure, a second semiconductor structure, and an isolation structure which is disposed between the first and second semiconductor structures, and which includes a dielectric material having a dielectric constant higher than 8 and lower than 16. A method for manufacturing the device is also disclosed.
1 . A method comprising:
forming semiconductor structures each including a nanosheet stack which includes at least one first nanosheet, at least one second nanosheet alternating with the at least one first nanosheet;
forming an isolation structure between two adjacent ones of the semiconductor structures, the isolation structure including an isolation feature including a rare-earth element;
forming a gate structure over the semiconductor structures and the isolation structure such that each of the semiconductor structures has two exposed portions at two opposite sides of the gate structure, the gate structure including a dummy dielectric, a dummy gate disposed on the dummy dielectric, and two gate spacers disposed at two opposite sides of a dummy stack of the dummy gate and the dummy dielectric;
forming two source/drain recesses respectively in the exposed portions of each of the semiconductor structures to form the at least one first nanosheet into at least one first nanosheet segment, and to form the at least one second nanosheet into at least one second nanosheet segment;
recessing a first portion of the isolation feature which is exposed from the gate structure after forming the two source/drain recesses;
removing end regions of the at least one second nanosheet segment to form lateral recesses so as to leave a remaining region of the at least one second nanosheet segment;
forming inner spacers respectively in the lateral recesses;
forming two source/drain portions respectively in the source/drain recesses of each of the semiconductor structures;
removing the dummy gate and the dummy dielectric;
removing the remaining region of the at least one second nanosheet segment;
after removing the dummy dielectric and before removing the remaining region of the at least one second nanosheet segment, trimming a second portion of the isolation feature which is exposed after removal of the dummy dielectric; and
forming a gate portion to surround the at least one first nanosheet segment of each of the semiconductor structures, the gate portion including a gate electrode and a gate dielectric having a first dielectric region that is disposed to separate the gate electrode from the at least one first nanosheet segment of a corresponding one of the semiconductor structures, and a second dielectric region that is disposed to separate the gate electrode from the two source/drain portions formed on a corresponding one of the semiconductor structures.
2 . The method as claimed in claim 1 , wherein:
the isolation structure further includes an isolation body including a dielectric material that has a dielectric constant lower than a dielectric constant of the isolation feature;
the isolation feature is disposed on the isolation body so as to prevent damage of the isolation body when forming the source/drain recesses; and
in forming the semiconductor structures, two sacrificial portions are disposed to respectively cover two opposite sides of the nanosheet stack of each of the semiconductor structures.
3 . The method as claimed in claim 2 , further comprising:
removing lateral parts of the sacrificial portions to leave sacrificial bodies when forming the source/drain recesses;
in removing end regions of the at least one second nanosheet segment, removing end regions of the sacrificial bodies to form inner gaps; and
in forming the inner spacers, forming other inner spacers respectively in the inner gaps.
4 . The method as claimed in claim 3 , further comprising:
etching back the gate spacers after removing the dummy gate.
5 . A method comprising:
forming semiconductor structures respectively on substrate segments, each of the substrate segments being spaced apart from each other, each of the semiconductor structures including a material stack having first layers and second layers that alternate with the first layers;
forming a trench isolation element between the substrate segments;
forming an isolation structure over the trench isolation element between the semiconductor structures, the isolation structure including a first dielectric material which has a dielectric constant higher than 8 and lower than 16;
forming a gate structure over the semiconductor structures and the isolation structure, the gate structure including a dummy dielectric and a dummy gate, each of the semiconductor structures having two exposed portions exposed from the gate structure;
removing the two exposed portions to form source/drain recesses, the first layers and the second layers being formed into first segments and second segments, respectively;
forming source/drain portions in the source/drain recesses, respectively;
removing the dummy gate and the dummy dielectric;
removing the second segments; and
after removing the second segments, the dummy dielectric and the dummy gate, forming a metal gate structure around the first segments,
wherein the isolation structure includes an isolation feature that includes the first dielectric material, and an isolation body that includes a second dielectric material having a dielectric
wherein the isolation feature is disposed on the isolation body, and
wherein the isolation feature includes
an outer element that includes the first dielectric material, and
an inner element that includes a third dielectric material having a dielectric constant lower than a dielectric constant of the first dielectric material.
6 . The method as claimed in claim 5 , wherein the first dielectric material includes a rare-earth element.
7 . The method as claimed in claim 5 , wherein after forming the gate structure, the isolation feature has an isolation element covered by the gate structure and two lateral elements without being covered by the gate structure.
8 . The method as claimed in claim 7 , the method further comprising:
removing the two lateral elements after forming the source/drain recesses; and
forming contact etch stop layers and interlayer dielectrics after forming the source/drain portions.
9 . The method as claimed in claim 7 , further comprising trimming the isolation element after removing the dummy gate and the dummy dielectric, and prior to removing the second segments.
10 . The method as claimed in claim 9 , wherein after trimming the isolation element, an upper surface of the trimmed isolation element has a dimension smaller than a lower surface of the trimmed isolation element.
11 . The method as claimed in claim 7 , further comprising trimming the isolation elements after removing the dummy gate, the dummy dielectric, and the second segments.
12 . A method comprising:
forming semiconductor structures respectively on substrate segments, each of the substrate segments being spaced apart from each other, each of the semiconductor structures including a material stack having first layers and second layers that alternate with the first layers;
forming an isolation structure between the semiconductor structures, the isolation structure including an isolation feature which includes a first dielectric material;
forming a gate structure over the semiconductor structures and the isolation structure, the gate structure including a dummy dielectric and a dummy gate, each of the semiconductor structures having two exposed portions exposed from the gate structure, the isolation structure having an isolation element covered by the gate structure and two lateral elements without being covered by the gate structure;
removing the exposed portions to form source/drain recesses, the first layers and the second layers being formed into first segments and second segments, respectively; and
after forming the source/drain recesses, removing the two lateral elements of the isolation structure.
13 . The method as claimed in claim 12 , wherein
the isolation feature includes the isolation element and the two lateral elements, and the first dielectric material includes a rare-earth element,
the isolation structure further includes an isolation body that includes a second dielectric material having a dielectric constant lower than a dielectric constant of the first dielectric material and that is covered by the isolation feature, and
removing the two lateral elements includes removing upper parts of the two lateral elements during forming the source/drain recesses, leaving remaining parts of the two lateral elements covering the isolation body during forming the source/drain recesses.
14 . The method as claimed in claim 13 , wherein in forming the source/drain recesses, a reactive-ion etching process is used to permit ions of a halogen element to react with the rare-earth element so as to form a by-product layer over the remaining parts of the two lateral elements, the by-product layer including REX j , where RE refers to the rare-earth element, X refers to the halogen element, and j is a positive number.
15 . The method as claimed in claim 14 , further comprising forming contact etch stop layers and interlayer dielectrics after forming the source/drain portions,
wherein the by-product layer and the remaining parts of the two lateral elements are removed after forming the source/drain recesses and before forming the contact etch stop layers and interlayer dielectrics.
16 . The method as claimed in claim 13 , wherein the isolation body includes a dielectric film, and a dielectric body surrounded by the dielectric film, a material of the dielectric film being different from a material of the dielectric body.
17 . The method as claimed in claim 12 , further comprising:
forming source/drain portions in the source/drain recesses, respectively;
removing the dummy gate and the dummy dielectric;
removing the second segments; and
after removing the second segments, the dummy dielectric and the dummy gate, forming a metal gate structure around the first segments.
18 . The method as claimed in claim 17 , further comprising trimming the isolation feature after completely removing the second segments.
19 . The method as claimed in claim 12 , wherein
the isolation structure further includes an isolation body including a second dielectric material having a dielectric constant lower than a dielectric constant of the first dielectric material, the isolation body being separated from the semiconductor structures by the isolation feature, and
an upper portion of the isolation body and an upper portion of the isolation feature together form a combination of the isolation element and the two lateral elements.
20 . The method as claimed in claim 12 , wherein the first dielectric material has a dielectric constant higher than 8 and lower than 16.