Extended lower source/drain for stacked field-effect transistor
Embodiments herein include semiconductor structures with an active channel stack having an upper field-effect transistor (FET) and a lower FET vertically stacked below the upper FET The semiconductor structure may also include a dummy stub adjacent to the active channel stack, a lower source/drain (S/D) connected to the active channel stack and laterally extended over the dummy stub, and an upper S/D connected to the active channel stack above the lower S/D.
1 . A semiconductor structure, comprising:
an active channel stack comprising an upper field-effect transistor (FET) and a lower FET vertically stacked below the upper FET;
a dummy stub adjacent to the active channel stack and protruding between shallow trench isolations (STIs) in a gate region;
a lower source/drain (S/D) connected to the active channel stack and laterally extended over the dummy stub; and
an upper S/D connected to the active channel stack above the lower S/D.
2 . The semiconductor structure of claim 1 , further comprising:
a lower S/D contact located above the dummy stub; and
an upper S/D contact located above the active channel stack.
3 . The semiconductor structure of claim 1 , wherein the active channel stack comprises a fin FET.
4 . The semiconductor structure of claim 3 , further comprising a dielectric liner above the dummy stub, wherein the dielectric liner surrounds a high-κ metal gate and a work-function metal (WFM).
5 . The semiconductor structure of claim 4 , wherein the dielectric liner isolates the high-κ metal gate and the WFM from the lower S/D and the upper S/D.
6 . The semiconductor structure of claim 1 , wherein the upper FET is a nanosheet FET.
7 . The semiconductor structure of claim 6 , further comprising a dielectric isolation structure between the upper FET and the lower FET.
8 . The semiconductor structure of claim 6 , wherein the active channel stack comprises a lateral width that is greater than a lateral width of the the dummy stub.
9 . A method, comprising:
forming an active channel stack and a dummy stack adjacent to the active channel stack;
growing a lower source/drain (S/D) across the active channel stack and the dummy stack;
growing a first top S/D on the active channel stack and a second top S/D on the dummy stack; and
removing the dummy stack except for a dummy stub that protrudes between the shallow trench isolations (STIs).
10 . The method of claim 9 , wherein forming the active channel stack comprises forming a fin field-effect transistor (fin FET).
11 . The method of claim 10 , wherein the dummy stack comprises a fin structure adjacent to the fin FET.
12 . The method of claim 10 , wherein removing the dummy stack comprises forming a gap within a shallow trench isolation (STI) structure over the dummy stub.
13 . The method of claim 12 , further comprising forming a dielectric liner in the gap, wherein the dielectric liner surrounds a high-κ metal gate and a work-function metal (WFM).
14 . The method of claim 9 , further comprising forming a lower contact through the second top S/D to the lower S/D.
15 . The method of claim 9 , wherein forming the active channel stack comprises forming a nanosheet field-effect transistor (FET).
16 . The method of claim 15 , wherein the active channel stack comprises a lateral width that is greater than a lateral width of the dummy stack.
17 . A semiconductor structure, comprising:
an upper source/drain (S/D) electrically connected to an active channel stack;
a lower S/D electrically connected to the active channel stack, wherein the lower S/D comprises:
a first growth between the upper S/D and the active channel stack; and
a second growth between a dummy stub and a contact, wherein the dummy stub protrudes up from the substrate between shallow trench isolations (STIs) in a gate region.
18 . The semiconductor structure of claim 17 , further comprising:
a lower S/D contact located above the dummy stub; and
an upper S/D contact located above the active channel stack.
19 . The semiconductor structure of claim 17 , wherein the active channel stack comprises a fin field-effect transistor (fin FET).
20 . The semiconductor structure of claim 17 , wherein the active channel stack comprises a nanosheet field-effect transistor (FET).