Bond enhancement structure in microelectronics for trapping contaminants during direct-bonding processes
Structures and techniques provide bond enhancement in microelectronics by trapping contaminants and byproducts during bonding processes, and arresting cracks. Example bonding surfaces are provided with recesses, sinks, traps, or cavities to capture small particles and gaseous byproducts of bonding that would otherwise create detrimental voids between microscale surfaces being joined, and to arrest cracks. Such random voids would compromise bond integrity and electrical conductivity of interconnects being bonded. In example systems, a predesigned recess space or predesigned pattern of recesses placed in the bonding interface captures particles and gases, reducing the formation of random voids, thereby improving and protecting the bond as it forms. The recess space or pattern of recesses may be placed where particles collect on the bonding surface, through example methods of determining where mobilized particles move during bond wave propagation. A recess may be repeated in a stepped reticule pattern at the wafer level, for example, or placed by an aligner or alignment process.
1. An apparatus, comprising:
a first bonding surface of a microelectronic component, the first bonding surface including a first dielectric material;
a second bonding surface directly bonded with the first bonding surface, the second bonding surface including a second dielectric material;
at least one recessed non-bonded area containing no electrically operational elements, the at least one recessed non-bonded area being disposed in, and bounded by, either the first dielectric material of the first bonding surface or second dielectric material of the second bonding surface, the at least one recessed non-bonded area comprising a first recess surrounding a central portion of the first bonding surface, and the first bonding surface further comprising a peripheral portion of the first bonding surface.
2. The apparatus of claim 1 , wherein recesses in the first bonding surface align with recesses in the second bonding surface.
3. The apparatus of claim 1 , further comprising a coating or a deposition of absorption, adsorption or occlusion material in the at least one recessed non-bonded area to absorb, adsorb, or occlude a bonding or annealing byproduct.
4. The apparatus of claim 1 , wherein the at least one recessed non-bonded area further comprises a second recess surrounding the peripheral portion of the first bonding surface.
5. The apparatus of claim 1 , wherein the first and second bonding surfaces comprise metal contacts, and the first and second bonding surfaces are direct hybrid bonded.
6. A direct hybrid bonded apparatus, comprising:
a first bonding surface of a first microelectronic component;
first conductors disposed at the first bonding surface, the first conductors positioned to make electrical contacts;
a second bonding surface of a second microelectronic component directly bonded with the first bonding surface at a bond interface;
second conductors disposed at the second bonding surface, the second conductors directly bonded with respective ones of the first conductors disposed at the first bonding surface;
a recessed metal pad below the first bonding surface, the recessed metal pad being a dummy pad unconnected to circuitry, the recessed metal pad being laterally wider than the first conductors, the recessed metal pad being sufficiently recessed relative to the first bonding surface to maintain a vertical gap between the recessed metal pad and the second bonding surface in the direct hybrid bonded apparatus.
7. The apparatus of claim 6 , wherein the recessed metal pad has a dished surface characteristic of chemical-mechanical planarization (CMP) of the first bonding surface.
8. The apparatus of claim 6 , further comprising a second recessed metal pad below the second bonding surface, the second recessed metal pad being laterally wider than the second conductors.
9. The apparatus of claim 8 , wherein the recessed metal pad below the first bonding surface and the second recessed metal pad below the second bonding surface overlap partially or fully to form a merged vertical gap across the bonding interface.
10. The apparatus of claim 6 , wherein the recessed metal pad is recessed relative to the first bonding surface greater than a thickness of the recessed metal pad.
11. A bonding structure for components of microelectronic devices, comprising:
a first bonding surface of a wafer or die, the first bonding surface including a first dielectric material;
a first recessed non-bonding area surrounding most or all of the first bonding surface, the first recessed non-bonding area comprising an etched recess in the first dielectric material and containing no metal connected to circuitry; and
a second bonding surface of the wafer or die surrounding most or all of the first recessed non-bonding area.
12. The bonding structure of claim 11 , wherein the etched recess contains byproducts and contaminants detrimental to the bonding process.
13. The bonding structure of claim 11 , further comprising another wafer or another die with an instance of the first bonding surface, the first recessed non-bonding area, the second bonding surface, and a second recessed non-bonding area on at least one side of the another wafer or die, for creating stacked bonded structures.
14. The bonding structure of claim 11 , further comprising additional recesses in the first bonding surface and the second bonding surface to arrest propagation of a debonding process or a delamination process in the first bonding surface or the second bonding surface.
15. The bonding structure of claim 11 , further comprising ribs between the first bonding surface and the second bonding surface to connect the first bonding surface and the second bonding surface into a continuous bonding area, the ribs facilitating bond propagation during a bonding process and increasing an overall bonding area.
16. The bonding structure of claim 11 , further comprising conductive traces running at least horizontally across the first recessed non-bonding area, the etched recess configured to impart a reduced dielectric loss and a reduced capacitive loss to signals of the conductive traces.
17. The bonding structure of claim 11 , further comprising metal contacts in the first bonding surface, the first bonding surface being planarized and suitable for direct hybrid bonding.
18. An apparatus, comprising:
a first bonding area of a wafer or die, the first bonding area configured for direct bonding and including a dielectric material;
a second bonding area of the wafer or die, the second bonding area surrounding the first bonding area, including the dielectric material, and configured for direct bonding;
a first recessed non-bonding area at least substantially surrounding the first bonding area, the first recessed non-bonding area comprising at least one etched recess bounded by the dielectric material and separating the first bonding area from the second bonding area; and
a second recessed non-bonding area disposed along an entire outer perimeter of the wafer or die, surrounding the second bonding area.
19. An apparatus according to claim 18 , further comprising conductive traces traversing the first and/or second recessed non-bonding areas.
20. An apparatus according to claim 18 , wherein the first bonding area and/or the second bonding area comprises metal contacts and is configured for direct hybrid bonding.