IP Library › Granted Patent US 12,300,500
Granted Patent B2
US 12,300,500 · App. 17/690,715 · Granted May 13, 2025

Etching of polycrystalline semiconductors

Inventors: Yun Han (Albany, NY); Alok Ranjan (Austin, TX); Tomoyuki Oishi (Miyagi, JP); Shuhei Ogawa (Miyagi, JP); Ken Kobayashi (Miyagi, JP); Peter Biolsi (Albany, NY)
Assignee: Tokyo Electron Limited
H01L21/3065H10D84/0158H10D84/038
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Quick Facts
Patent No.
US 12,300,500
App. No.
17/690,715
Granted
May 13, 2025
Kind
B2
Abstract

A method of processing a substrate that includes: performing a cyclic plasma etch process including a plurality of cycles, each of the plurality of cycles including: etching a patterning layer including a polycrystalline semiconductor material to form or extend a recess by exposing the substrate to a first plasma, the substrate including an oxide layer, the patterning layer formed over the oxide layer, exposing the substrate to a second plasma, the second plasma including dihydrogen, and extending the recess by exposing the substrate to a third plasma, the second plasma being different from the first plasma and the third plasma.

Claims (39)

1. A method of processing a substrate, the method comprising:

performing a cyclic plasma etch process comprising a plurality of cycles, each of the plurality of cycles comprising:

etching a patterning layer comprising a polycrystalline semiconductor material to form or extend a recess by exposing the substrate to a first plasma, the substrate comprising an oxide layer, the patterning layer formed over the oxide layer, and

exposing the substrate to a second plasma, the second plasma comprising dihydrogen, wherein exposing the substrate to the second plasma amorphizes the polycrystalline semiconductor material at surfaces of the recess; and

extending the recess by exposing the substrate to a third plasma, the second plasma being different from the first plasma and the third plasma.

2. The method of claim 1 , further comprising, before performing the cyclic plasma etch process, forming a patterned hard mask layer over the patterning layer by a lithographic process and an etch, and wherein the cyclic plasma etch process is performed using the patterned hard mask layer as an etch mask.

3. The method of claim 1 , further comprising, after performing the cyclic plasma etch process and before extending the recess by exposing the substrate to the third plasma, performing a surface treatment to form a protective surface layer on the surfaces of the recess, the protective surface layer protecting sidewalls of the recess during extending the recess by exposing the substrate to the third plasma.

4. The method of claim 3 , wherein the surface treatment comprises exposing the substrate to a reactive gas, the reactive gas comprising oxygen, and wherein the protective surface layer comprise an oxide.

5. The method of claim 3 , wherein the surface treatment comprises exposing the substrate to a reactive gas, the reactive gas comprising nitrogen, and wherein the protective surface layer comprise a nitride.

6. The method of claim 1 , wherein the first plasma comprises a halogen.

7. The method of claim 6 , wherein the first plasma comprises hydrogen bromide and dichlorine.

8. The method of claim 1 , wherein exposing the substrate to the second plasma smoothens surfaces of sidewalls of the recess.

9. The method of claim 1 , wherein the third plasma comprises a halogen.

10. The method of claim 1 , wherein the third plasma comprises hydrogen bromide and dichlorine.

11. The method of claim 1 , wherein an etch rate of the polycrystalline semiconductor material during exposing the substrate to the third plasma is slower than an etch rate of the polycrystalline semiconductor material during exposing the substrate to the first plasma.

12. The method of claim 1 , wherein the recess extended by exposing the substrate to the third plasma has a height-to-width ratio between about 5 to 10.

13. The method of claim 1 , wherein the second plasma is a hydrogen plasma generated from dihydrogen.

14. A method of processing a substrate, the method comprising:

performing a cyclic plasma etch process comprising a plurality of cycles, each of the plurality of cycles comprising:

etching a polysilicon layer to form a recess by exposing the substrate to a first plasma for a first duration, the substrate comprising an oxide layer, the polysilicon layer formed over the oxide layer, the first plasma comprising hydrogen bromide and dichlorine, and

exposing the substrate to a second plasma for a second duration, the second plasma comprising dihydrogen, wherein exposing the substrate to the second plasma smoothens surfaces of sidewalls of the recess.

15. The method of claim 14 , wherein the first duration is between 5 s to 120 s, and wherein the second duration is between 2 s to 50 s.

16. The method of claim 14 , wherein exposing the substrate to the second plasma amorphizes the polysilicon layer at surfaces of the recess and reduce a standard deviation of critical dimensions of the recess at different depths by 20% or more.

17. The method of claim 14 , further comprising, after performing the cyclic plasma etch process:

performing a surface treatment to form a protective surface layer on surfaces of the recess; and

further extending the recess in the polysilicon layer by an etch process comprising exposing the substrate comprising a third plasma for a third duration, the third plasma comprising hydrogen bromide and dichlorine, the protective surface layer protecting the sidewalls of the recess from the third plasma.

18. The method of claim 17 , wherein the third duration is longer than the first duration.

19. A method of fabricating a fin field-effect transistor, the method comprising:

forming a fin feature over an oxide layer, the oxide layer formed over a substrate, the fin feature comprising a fin hard mask and a fin under the fin hard mask, the fin comprising silicon;

depositing a dummy gate material comprising polysilicon;

depositing a gate hard mask layer over the dummy gate material;

depositing a photoresist over the gate hard mask layer;

performing a photolithographic process to pattern the photoresist;

etching the gate hard mask layer to transfer a pattern from the photoresist to the gate hard mask layer; and

performing a cyclic plasma etch process using the gate hard mask layer as an etch mask, the cyclic plasma etch process exposing the fin hard mask, the cyclic plasma etch process comprising a plurality of cycles, each of the plurality of cycles comprising:

etching the dummy gate material to form a recess by exposing the substrate to a first plasma, the first plasma comprising a halogen; and

exposing the substrate to a second plasma, the second plasma comprising hydrogen, wherein exposing the substrate to the second plasma smoothens surfaces of sidewalls of the recess.

20. The method of claim 19 , further comprising, after performing the cyclic plasma etch process, extending the recess by exposing the substrate to a third plasma, the third plasma comprising a halogen, wherein performing the cyclic plasma etch process exposes top surfaces of the fin hard mask, and wherein extending the recess by exposing the substrate to the third plasma exposes the oxide layer.

21. The method of claim 19 , wherein exposing the substrate to the second plasma amorphizes the dummy gate material at surfaces of the recess.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 9, 2022
From: HAN, YUN; RANJAN, ALOK; OISHI, TOMOYUKI; OGAWA, SHUHEI; KOBAYASHI, KEN; BIOLSI, PETER
To: TOKYO ELECTRON LIMITED
Reel/Frame 059213/0141 →
Continuity (1)
Related Publication 20230317462A1 · Oct 5, 2023
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