IP Library › Granted Patent US 12,224,224
Granted Patent B2
US 12,224,224 · App. 17/693,444 · Granted Feb 11, 2025

Package structure with metallic layer over the surfaces of a plurality of semiconductor dies

Inventors: Chih-Hao Chen (Taipei, TW); Po-Yuan Cheng (New Taipei, TW); Pu Wang (Hsinchu, TW); Li-Hui Cheng (New Taipei, TW)
Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
H01L23/3736H01L21/4857H01L21/4871H01L21/563H01L23/3107H01L23/49822H01L23/5381H01L24/32H01L25/0657H01L2224/32225H01L2924/181
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Quick Facts
Patent No.
US 12,224,224
App. No.
17/693,444
Granted
Feb 11, 2025
Kind
B2
Abstract

A package structure includes first and second package components, an underfill layer disposed between the first and second package components, and a metallic layer. The first package component includes semiconductor dies, a first insulating encapsulation laterally encapsulating the semiconductor dies, and a redistribution structure underlying first surfaces of the semiconductor dies and the first insulating encapsulation. The second package component underlying the first package component is electrically coupled to the semiconductor dies through the redistribution structure. The underfill layer extends to cover a sidewall of the first package component, the metallic layer overlying second surfaces of the semiconductor dies and the first insulating encapsulation, and a peripheral region of the second surface of the first insulating encapsulation is accessibly exposed by the metallic layer, where the first surfaces are opposite to the second surfaces. A manufacturing method of a package structure is also provided.

Claims (50)

1. A package structure, comprising:

a first package component comprising:

semiconductor dies, each of the semiconductor dies comprising a first surface and a second surface opposite to each other;

a first insulating encapsulation laterally encapsulating the semiconductor dies; and

a redistribution structure underlying the first surfaces of the semiconductor dies and a first surface the first insulating encapsulation, and the redistribution structure being electrically coupled to the semiconductor dies; and

a second package component underlying the first package component and electrically coupled to the semiconductor dies through the redistribution structure;

a first underfill layer disposed between the first and second package components and extending to cover a sidewall of the first package component; and

a metallic layer overlying the second surfaces of the semiconductor dies and a second surface of the first insulating encapsulation, wherein the first surface and the second surface of the first insulating encapsulation are opposite to each other, and a peripheral region of the second surface of the first insulating encapsulation is accessibly exposed by the metallic layer, wherein in a top view, the metallic layer comprises a rounded corner that corresponds to a corner at the intersection between two adjacent sides of the first insulating encapsulation, and a width of the peripheral region between sides of the metallic layer and the first insulating encapsulation is less than a width of the peripheral region between the corner of the first insulating encapsulation and the rounded corner of the metallic layer.

2. The package structure of claim 1 , wherein in the top view, a boundary of the metallic layer is encircled by a boundary of the first package component, and the boundary of the first package component is encircled by a boundary of the first underfill layer.

3. The package structure of claim 1 , wherein the width of the peripheral region between the sides of the metallic layer and the first insulating encapsulation is greater than a thickness of the metallic layer.

4. The package structure of claim 1 , wherein a top-view shape of the metallic layer is different from that of the first insulating encapsulation.

5. The package structure of claim 1 , wherein the first surfaces of the semiconductor dies and the first surface the first insulating encapsulation are substantially leveled, and the second surfaces of the semiconductor dies and the second surface the first insulating encapsulation are substantially leveled.

6. The package structure of claim 1 , wherein the first package component further comprises:

a bridge die underlying the redistribution structure and below adjacent two of the semiconductor dies, the bridge die being electrically coupled to the adjacent two of the semiconductor dies through the redistribution structure;

a second insulating encapsulation underlying the redistribution structure and covering the bridge die; and

through interlayer vias penetrating through the second insulating encapsulation and electrically coupled to the semiconductor dies through the redistribution structure.

7. The package structure of claim 6 , wherein the first package component further comprises:

a second underfill layer disposed between the bridge die and the redistribution structure, wherein a tapering direction of the second underfill layer is opposite to that of the first underfill layer in a cross-sectional view.

8. The package structure of claim 1 , further comprising:

a thermal interface material layer overlying the metallic layer and physically covering the peripheral region of the first insulating encapsulation; and

a heat dissipating component thermally coupled to the first package component through the metallic layer and the thermal interface material layer.

9. A package structure, comprising:

a first package component comprising:

semiconductor dies, each of the semiconductor dies comprising a first surface and a second surface opposite to each other;

an insulating encapsulation laterally encapsulating the semiconductor dies; and

a redistribution structure underlying the first surfaces of the semiconductor dies and a first surface the insulating encapsulation, and the redistribution structure being electrically coupled to the semiconductor dies;

a second package component underlying the first package component and electrically coupled to the semiconductor dies through the redistribution structure;

an underfill layer disposed between the first and second package components and extending to cover a sidewall of the first package component; and

a metallic layer overlying the second surfaces of the semiconductor dies and a second surface of the insulating encapsulation, and the metallic layer further extending to cover the underfill layer wherein the metallic layer is in physical contact with a sidewall of the insulating encapsulation of the first package component and extends to be in physical contact with an outer surface of the underfill layer.

10. The package structure of claim 9 , wherein in a top view, a boundary of the first package component is encircled by a boundary of the metallic layer, and the boundary of the metallic layer is encircled by a boundary of the underfill layer.

11. The package structure of claim 9 , wherein in a top view, the metallic layer comprises a rounded corner that corresponds to a rounded corner of the underfill layer.

12. The package structure of claim 9 , wherein in a cross-sectional view, a width of the underfill layer measured from a sidewall of the first package component to an endpoint of the underfill layer on the second package component is greater than a width of the metallic layer measured from the sidewall of the first package component to an endpoint of the metallic layer on the underfill layer.

13. The package structure of claim 9 , wherein in a cross-sectional view, a thickness of the metallic layer overlying the underfill layer decreases from a corner of the first package component to an endpoint of the metallic layer on the underfill layer.

14. The package structure of claim 9 , wherein the underfill layer covers an entirety of a sidewall of the insulating encapsulation.

15. The package structure of claim 9 , wherein the first surfaces of the semiconductor dies and the first surface the first insulating encapsulation are substantially leveled.

16. The package structure of claim 9 , further comprising:

a thermal interface material layer disposed over the first package component and overlying the metallic layer, and the thermal interface material layer accessibly exposing at least a portion of the metallic layer on the underfill layer; and

a heat dissipating component thermally coupled to the first package component through the metallic layer and the thermal interface material layer.

17. A package structure, comprising:

a first package component comprising:

semiconductor dies;

an insulating encapsulation laterally encapsulating the semiconductor dies; and

a second package component underlying the first package component and electrically coupled to the semiconductor dies;

an underfill layer disposed between the first and second package components; and

a metallic layer overlying rear surfaces of the semiconductor dies and a surface of the insulating encapsulation, wherein the surface of the insulating encapsulation and the rear surfaces of the semiconductor dies are substantially leveled with one another, and a peripheral region of the surface of the insulating encapsulation is accessibly exposed by the metallic layer, wherein in a top view, the metallic layer comprises a rounded corner that corresponds to a rounded corner of the underfill layer.

18. The package structure of claim 17 , wherein in the top view, a boundary of the metallic layer is encircled by a boundary of the first package component, and the boundary of the first package component is encircled by a boundary of the underfill layer.

19. The package structure of claim 17 , further comprising:

a thermal interface material layer overlying the metallic layer and the insulating encapsulation; and

a heat dissipating component thermally coupled to the first package component through the metallic layer and the thermal interface material layer.

20. The package structure of claim 17 , wherein in the top view, a curvature of the rounded corner of the metallic layer is different from a curvature of the rounded corner of the underfill layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 15, 2022
From: CHEN, CHIH-HAO; CHENG, PO-YUAN; WANG, PU; CHENG, LI-HUI
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 059261/0781 →
Continuity (1)
Related Publication 20230290704A1 · Sep 14, 2023
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