Semiconductor memory device
A semiconductor memory device includes a substrate including a first region and a second region arranged in a first direction, conductive layers arranged in a second direction and extending in the first direction, a semiconductor layer disposed in the first region and opposed to the conductive layers, contact electrodes disposed in the second region and electrically connected to the conductive layers, and a first structure connected to a first contact electrode in the contact electrodes and a terrace portion of a first conductive layer in the conductive layers. The first structure includes a first conductive portion, a second conductive portion, and a third conductive portion. The first conductive portion extends in the first direction. The second conductive portion and the third conductive portion are connected to one end portion or the other end portion of the first conductive portion in the first direction and the first conductive layer.
1. A semiconductor memory device comprising:
a substrate including a first region and a second region arranged in a first direction;
a plurality of conductive layers and a plurality of insulating layers alternately arranged in a second direction intersecting with a surface of the substrate and extending in the first direction across the first region and the second region;
a semiconductor layer disposed in the first region, extending in the second direction, and opposed to the plurality of conductive layers;
an electric charge accumulating film disposed between the plurality of conductive layers and the semiconductor layer;
a plurality of contact electrodes disposed in the second region, extending in the second direction, and electrically connected to the plurality of conductive layers; and
a first structure connected to one end portion in the second direction of a first contact electrode which is one of the plurality of contact electrodes and connected to a terrace portion of a first conductive layer which is one of the plurality of conductive layers, wherein
the first structure includes:
a first conductive portion extending in the first direction;
an intermediate conductive portion disposed between the first conductive layer and the first conductive portion and extending in the first direction;
a second conductive portion extending in the second direction and connected to one end portion of the first conductive portion in the first direction, one end portion of the intermediate conductive portion in the first direction, and the first conductive layer; and
a third conductive portion extending in the second direction and connected to the other end portion of the first conductive portion in the first direction, the other end portion of the intermediate conductive portion in the first direction, and the first conductive layer, and
the intermediate conductive portion is disposed at a position corresponding to a second conductive layer in the second direction, the second conductive layer being another one of the plurality of conductive layers positioned closer to the other end portion of the first contact electrode than the first conductive layer in the second direction, the second conductive layer being adjacent to the first conductive layer in the second direction.
2. The semiconductor memory device according to claim 1 , wherein
a length of the first conductive portion in the second direction is larger than a length of the second conductive portion in the first direction.
3. The semiconductor memory device according to claim 1 , wherein
the first structure further includes a fourth conductive portion extending in the second direction and connected to one end portion of the first conductive portion in a third direction intersecting with the first direction and the second direction, one end portion of the intermediate conductive portion in the third direction, and the first conductive layer.
4. The semiconductor memory device according to claim 3 , wherein
a length of the first conductive portion in the second direction is larger than a length of the fourth conductive portion in the third direction.
5. The semiconductor memory device according to claim 1 , wherein
a length of the first conductive portion in the second direction is larger than a length of the intermediate conductive portion in the second direction.
6. The semiconductor memory device according to claim 1 , wherein
the plurality of conductive layers further include a third conductive layer positioned closer to the other end portion of the first contact electrode than the second conductive layer in the second direction, and
a surface of the first conductive portion in the first conductive layer side in the second direction is disposed at a position corresponding to a surface of the third conductive layer in the first conductive layer side in the second direction.
7. The semiconductor memory device according to claim 1 , wherein
a length of the first conductive portion in the second direction is larger than a length of the first conductive layer in the second direction.
8. The semiconductor memory device according to claim 1 , wherein
a fifth conductive portion is disposed at a position corresponding to a terrace portion of the second conductive layer in the second direction, the fifth conductive portion being separated from the second conductive layer while being connected to the first conductive layer between the second conductive layer and the first contact electrode in the first direction.
9. The semiconductor memory device according to claim 1 , further comprising:
a second structure disposed in the second region, extending in the second direction, and having an outer peripheral surface connected to the first conductive layer, the first conductive portion, and the intermediate conductive portion.
10. A semiconductor memory device comprising:
a substrate including a first region and a second region arranged in a first direction;
a plurality of conductive layers and a plurality of insulating layers alternately arranged in a second direction intersecting with a surface of the substrate and extending in the first direction across the first region and the second region;
a semiconductor layer disposed in the first region, extending in the second direction, and opposed to the plurality of conductive layers;
an electric charge accumulating film disposed between the plurality of conductive layers and the semiconductor layer;
a plurality of contact electrodes disposed in the second region, extending in the second direction, and electrically connected to the plurality of conductive layers; and
a first structure connected to one end portion in the second direction of a first contact electrode which is one of the plurality of contact electrodes and a terrace portion of a first conductive layer which is one of the plurality of conductive layers, wherein
the first structure includes:
a first conductive portion extending in the first direction;
an intermediate conductive portion disposed between the first conductive layer and the first conductive portion and extending in the first direction; and
a second conductive portion extending in the second direction and connected to the first conductive portion, the intermediate conductive portion, and the first conductive layer,
both end portions of the first structure in a third direction intersecting with the first direction and the second direction are disposed between both end portions of the terrace portion of the first conductive layer in the third direction viewed in the second direction, and
the intermediate conductive portion is disposed at a position corresponding to a second conductive layer in the second direction, the second conductive layer being another one of the plurality of conductive layers positioned closer to the other end portion of the first contact electrode than the first conductive layer in the second direction, the second conductive layer being adjacent to the first conductive layer in the second direction.
11. The semiconductor memory device according to claim 10 , wherein
both end portions of the first structure in the first direction are disposed between both end portions of the terrace portion of the first conductive layer in the first direction viewed in the second direction.
12. The semiconductor memory device according to claim 10 , wherein
the first structure further includes a third conductive portion extending in the second direction and connected to the first conductive portion, the intermediate conductive portion, and the first conductive layer,
the second conductive portion is connected to one end portion of the first conductive portion in the third direction, one end portion of the intermediate conductive portion in the third direction, and the first conductive layer, and
the third conductive portion is connected to the other end portion of the first conductive portion in the third direction, the other end portion of the intermediate conductive portion in the third direction, and the first conductive layer.
13. The semiconductor memory device according to claim 10 , wherein
the plurality of conductive layers further include a third conductive layer positioned closer to the other end portion of the first contact electrode than the second conductive layer in the second direction, and
a surface of the first conductive portion in the first conductive layer side in the second direction is disposed at a position corresponding to a surface of the third conductive layer in the first conductive layer side in the second direction.
14. The semiconductor memory device according to claim 10 , wherein
a length of the first conductive portion in the second direction is larger than a length of the first conductive layer in the second direction.
15. The semiconductor memory device according to claim 10 , wherein
a fourth conductive portion is disposed at a position corresponding to a terrace portion of the second conductive layer in the second direction, the fourth conductive portion being separated from the second conductive layer while being connected to the first conductive layer between the second conductive layer and the first contact electrode in the first direction.
16. The semiconductor memory device according to claim 10 , further comprising:
a second structure disposed in the second region, extending in the second direction, and having an outer peripheral surface connected to the first conductive layer, first conductive portion, and the intermediate conductive portion.
17. The semiconductor memory device according to claim 1 , wherein
a length of the intermediate conductive portion in the second direction is substantially same as a length of the second conductive layer in the second direction.
18. The semiconductor memory device according to claim 10 , wherein
a length of the intermediate conductive portion in the second direction is substantially same as a length of the second conductive layer in the second direction.
19. The semiconductor memory device according to claim 1 , wherein
the plurality of insulating layers include:
a first insulating layer disposed on one surface in the second direction of the second conductive layer; and
a second insulating layer disposed on the other surface in the second direction of the second conductive layer,
a part of the first insulating layer is disposed between the first conductive layer and the intermediate conductive portion, and
a part of the second insulating layer is disposed between the intermediate conductive portion and the first conductive portion.
20. The semiconductor memory device according to claim 10 , wherein
the plurality of insulating layers include:
a first insulating layer disposed on one surface in the second direction of the second conductive layer; and
a second insulating layer disposed on the other surface in the second direction of the second conductive layer,
a part of the first insulating layer is disposed between the first conductive layer and the intermediate conductive portion, and
a part of the second insulating layer is disposed between the intermediate conductive portion and the first conductive portion.