Three-dimensional semiconductor structures
Methods, devices, systems, and apparatus for three-dimensional semiconductor structures are provided. In one aspect, a semiconductor device includes: a semiconductor substrate, multiple conductive layers vertically stacked on the semiconductor substrate, and multiple transistors. The multiple conductive layers include a first conductive layer, a second conductive layer, and a third conductive layer that are sequentially stacked together. The multiple transistors include a first transistor and a second transistor in the first conductive layer and a third transistor in the third conductive layer. Each transistor includes a first terminal, a second terminal, and a gate terminal. First terminals of the first, second, and third transistors are conductively coupled to a first conductive node in the second conductive layer.
1. A semiconductor device comprising:
a semiconductor substrate;
multiple conductive layers vertically stacked along a vertical direction on the semiconductor substrate, the multiple conductive layers comprising a first conductive layer, a second conductive layer, and a third conductive layer that are sequentially stacked together; and
multiple transistors comprising a first transistor and a second transistor in the first conductive layer and a third transistor in the third conductive layer, each transistor comprising a first terminal, a second terminal, and a gate terminal,
wherein first terminals of the first, second, and third transistors are conductively coupled to a first conductive node in the second conductive layer, and
wherein the multiple transistors further comprise: another second transistor in the third conductive layer, and wherein the first transistor and the third transistor are transistors of a first dopant type, and the second transistor and the another second transistor are transistors of a second dopant type that is different from the first dopant type.
2. The semiconductor device of claim 1 , wherein the first conductive layer and the third conductive layer are made of a first conductive material, and
wherein the second conductive layer is made of a second conductive material different from the first conductive material.
3. The semiconductor device of claim 1 , wherein the multiple transistors further comprise fourth, fifth, and sixth transistors,
wherein the fourth and sixth transistors are in the first conductive layer, and the fifth transistor is in the third conductive layer, and
wherein first terminals of the fourth, fifth, and sixth transistors are conductively coupled to a second conductive node in the second conductive layer.
4. The semiconductor device of claim 3 , further comprising a staircase region configured to separate the first conductive layer, the second conductive layer, and the third conductive layer into two parts that are conductively insulated from each other,
wherein the first transistor and the second transistor are in a first part of the first conductive layer, and the fourth transistor and the sixth transistor are in a second part of the first conductive layer,
wherein the first conductive node is in a first part of the second conductive layer, and the second conductive node is in a second part of the second conductive layer, and
wherein the third transistor is in a first part of the third conductive layer, and the fifth transistor is in a second part of the third conductive layer.
5. The semiconductor device of claim 4 , wherein the staircase region comprises first and second staircase sub-regions that are symmetrical to each other,
wherein the semiconductor device further comprises:
a first set of VIAs vertically penetrating through the first staircase sub-region and respectively coupling to conductive pads on the first parts of the first, second, and third conductive layers, and
a second set of VIAs vertically penetrating through the second staircase sub-region and respectively coupling to conductive pads on the second parts of the first, second, and third conductive layers.
6. The semiconductor device of claim 3 , further comprising a first metallic layer above the first, second, and third conductive layers,
wherein a first conductive line in the first metallic layer is configured to conductively couple the first conductive node to a gate terminal of the fourth transistor in the first conductive layer and a gate terminal of the fifth transistor in the third conductive layer, and
wherein a second conductive line in the first metallic layer is configured to conductively couple the second conductive node to a gate terminal of the second transistor in the first conductive layer and a gate terminal of the third transistor in the third conductive layer.
7. The semiconductor device of claim 6 , wherein second terminals of the first transistor and the sixth transistor in the first conductive layer are coupled to a pair of first signal lines formed in a second metallic layer,
wherein gate terminals of the first transistor and the sixth transistor in the first conductive layer are coupled to a second signal line formed in a third metallic layer, and
wherein the first metallic layer, the second metallic layer, and the third metallic layer are vertically stacked together above the multiple conductive layers.
8. The semiconductor device of claim 6 , wherein the first conductive line and the second conductive line are conductively insulated from each other in the first metallic layer and extend along a horizontal direction perpendicular to the vertical direction, and
wherein the first conductive line in the first metallic layer is respectively coupled to the gate terminal of the fourth transistor in the first conductive layer, the first conductive node in the second conductive layer, and the gate terminal of the fifth transistor in the third conductive layer with a first set of VIAs penetrating through a first staircase sub-region along the vertical direction, and
wherein the second conductive line in the first metallic layer is respectively coupled to the gate terminal of the second transistor in the first conductive layer, the second conductive node in the second conductive layer, and the gate terminal of the third transistor in the third conductive layer with a second set of VIAs penetrating through a second staircase sub-region along the vertical direction.
9. The semiconductor device of claim 3 , comprising a pair of inverters comprising a first inverter having the first, second, and third transistors and a second inverter having the fourth, fifth, sixth transistors, and
wherein the first and sixth transistors are pass gate transistors in the first and second inverters, respectively, the second and fourth transistors are pull up transistors in the first and second inverters, respectively, and the third and fifth transistors are pull down transistors in the first and second inverters, respectively.
10. The semiconductor device of claim 3 , wherein second terminals of the second transistor and the fourth transistor in the first conductive layer are conductive coupled to a first supply voltage, and
wherein second terminals of the third transistor and the fifth transistor in the third conductive layer are conductive coupled to a second supply voltage.
11. The semiconductor device of claim 3 , wherein the multiple transistors further comprise:
another fourth transistor in the third conductive layer that shares a gate terminal of the fifth transistor.
12. The semiconductor device of claim 3 , wherein gate terminals of the first transistor and the second transistor are conductively insulated from each other by a first insulating slit extending along the vertical direction through the first conductive layer onto the second conductive layer, and
wherein gate terminals of the fourth transistor and the sixth transistor are conductively insulated from each other by a second insulating slit extending along the vertical direction through the first conductive layer onto the second conductive layer.
13. The semiconductor device of claim 3 , configured to be a 6T SRAM cell.
14. The semiconductor device of claim 13 , wherein the 6T SRAM cell is coupled to a nonvolatile memory cell in a gate-all-around (GAA) transistor architecture.
15. The semiconductor device of claim 1 , wherein the first dopant type is N dopant type, and the second dopant type is P dopant type.
16. The semiconductor device of claim 1 , wherein the semiconductor substrate comprises a first doped region having the first dopant type and a second doped region having the second dopant type, the first doped region and the second doped region being conductively insulated from each other, and
wherein the semiconductor device comprises multiple semiconductor pillars extending through the multiple conductive layers onto the semiconductor substrate, and
wherein the multiple semiconductor pillars comprise a first semiconductor pillar extending onto the first doped region and a second semiconductor pillar extending onto the second doped region.
17. The semiconductor device of claim 16 , wherein each of the first semiconductor pillar and the second semiconductor pillar is surrounded by a gate dielectric structure in the first conductive layer and the third conductive layer, and
wherein each of the first semiconductor pillar and the second semiconductor pillar is surrounded by a metallic structure in the second conductive layer.
18. The semiconductor device of claim 17 , wherein the first semiconductor pillar comprises a first portion above the multiple conductive layers and a second portion surrounded by the metallic structure in the second conductive layer, and wherein the first portion and the second portion of the first semiconductor pillar are doped with the first dopant type, and
wherein the second semiconductor pillar comprises a third portion above the multiple conductive layers and a fourth portion surrounded by the metallic structure in the second conductive layer, and wherein the third portion and the fourth portion of the second semiconductor pillar are doped with the second dopant type.
19. The semiconductor device of claim 17 , wherein the first transistor comprises a first portion of the first conductive layer, a first portion of the second semiconductor pillar surrounded by a first gate dielectric structure in the first conductive layer, and the first gate dielectric structure,
wherein the second transistor comprises a second portion of the first conductive layer, a first portion of the first semiconductor pillar surrounded by a second gate dielectric structure in the first conductive layer, and the second gate dielectric structure, and
wherein the third transistor comprises a portion of the third conductive layer, a second portion of the second semiconductor pillar surrounded by a third gate dielectric structure in the third conductive layer, and the third gate dielectric structure.
20. The semiconductor device of claim 1 , configured to be between adjacent conductive slits extending along the vertical direction through the multiple conductive layers onto the semiconductor substrate.
21. A semiconductor device comprising:
a semiconductor substrate;
multiple conductive layers vertically stacked on the semiconductor substrate comprising a bottom conductive layer, a middle conductive layer, and a top conductive layer that are sequentially stacked together;
a first semiconductor pillar vertically penetrating through the multiple conductive layers onto the semiconductor substrate, the first semiconductor pillar comprising a first bottom portion surrounded by the bottom conductive layer, a first middle portion surrounded by the middle conductive layer, and a first top portion surrounded by the top conductive layer;
a second semiconductor pillar vertically penetrating through the multiple conductive layers onto the semiconductor substrate, the second semiconductor pillar comprising a second bottom portion surrounded by the bottom conductive layer, a second middle portion surrounded by the middle conductive layer, and a second top portion surrounded by the top conductive layer; and
a plurality of gate dielectric structures comprising a first gate dielectric structure surrounded by the first bottom portion and the bottom conductive layer and a second gate dielectric structure surrounded by the first top portion and the top conductive layer,
wherein the first middle portion of the first semiconductor pillar is conductively coupled to the middle conductive layer,
wherein the semiconductor substrate comprises a first region having a first dopant type and a second region having a second dopant type different from the first dopant type, wherein the first semiconductor pillar vertically extends onto the first region to form first junctions with the first dopant type, and the second semiconductor pillar vertically extends onto the second region to form second junctions with the second dopant type, and
wherein each of the first top portion and the first middle portion of the first semiconductor pillar is configured to be a corresponding first junction and is doped with a first material having the first dopant type, and each of the second top portion and the second middle portion is configured to be a corresponding second junction and is doped with a second material having the second dopant type.
22. The semiconductor device of claim 21 ,
wherein the plurality of gate dielectric structures comprising a third gate dielectric structure surrounded by the second bottom portion and the bottom conductive layer and a fourth gate dielectric structure surrounded by the second top portion and the top conductive layer, and
wherein the second middle portion of the second semiconductor pillar is conductively coupled to the middle conductive layer.
23. The semiconductor device of claim 22 , further comprising a plurality of metallic structures in the middle conductive layer,
wherein the plurality of metallic structures comprise:
a first metallic structure surrounded by the first middle portion of the first semiconductor pillar and the middle conductive layer, and
a second metallic structure surrounded by the second middle portion of the second semiconductor pillar and the middle conductive layer.
24. The semiconductor device of claim 22 , wherein the bottom conductive layer comprises: a first conductive portion surrounding the first gate dielectric structure and the first semiconductor pillar and a second conductive portion surrounding the third gate dielectric structure and the second semiconductor pillar, the first conductive portion and the second conductive portion at least partially overlapping with each other between the first gate dielectric structure and the second gate dielectric structure, and
wherein the top conductive layer comprises: a third conductive portion surrounding the second gate dielectric structure and the first semiconductor pillar and a fourth conductive portion surrounding the fourth gate dielectric structure and the second semiconductor pillar, the third conductive portion and the fourth conductive portion being separated and insulated from each other between the third gate dielectric structure and the fourth gate dielectric structure.
25. The semiconductor device of claim 22 , further comprising:
a third semiconductor pillar vertically penetrating through the multiple conductive layers onto the semiconductor substrate, the third semiconductor pillar comprising a third bottom portion in the bottom conductive layer, a third middle portion surrounded by the middle conductive layer, and a third top portion surrounded by the top conductive layer, wherein the plurality of gate dielectric structures comprising a fifth gate dielectric structure surrounded by the third bottom portion and the bottom conductive layer and a sixth gate dielectric structure surrounded by the third top portion and the top conductive layer, and wherein the third middle portion of the third semiconductor pillar is conductively coupled to the middle conductive layer; and
a fourth semiconductor pillar vertically penetrating through the multiple conductive layers onto the semiconductor substrate, the fourth semiconductor pillar comprising a fourth bottom portion in the bottom conductive layer, a fourth middle portion surrounded by the middle conductive layer, and a fourth top portion surrounded by the top conductive layer, wherein the plurality of gate dielectric structures comprising a seventh gate dielectric structure surrounded by the fourth bottom portion and the bottom conductive layer and an eighth gate dielectric structure surrounded by the fourth top portion and the top conductive layer, and wherein the fourth middle portion of the fourth semiconductor pillar is conductively coupled to the middle conductive layer.
26. The semiconductor device of claim 25 , further comprising a metallic layer above the multiple conductive layers,
wherein the middle conductive layer comprises a first portion where the first and second semiconductor pillars penetrate through and a second portion where the third and fourth semiconductor pillars penetrate through, the first portion and the second portion being insulated from each other,
wherein a first conductive line in the metallic layer is configured to conductively couple the first portion of the middle conductive layer to a portion of the top conductive layer surrounding the fourth semiconductor pillar and the eighth gate dielectric structure and a portion of the bottom conductive layer surrounding the third semiconductor pillar and the fifth gate dielectric structure, and
wherein a second conductive line in the metallic layer is configured to conductively couple the second portion of the middle conductive layer to a portion of the top conductive layer surrounding the first semiconductor pillar and the third gate dielectric structure and a portion of the bottom conductive layer surrounding the second semiconductor pillar and the second gate dielectric structure.
27. A memory device comprising:
a plurality of memory cells on a semiconductor substrate; and
a metallic layer formed above the plurality of memory cells,
wherein each of the plurality of memory cells comprises:
multiple conductive layers vertically stacked on the semiconductor substrate, the multiple conductive layers comprising a first conductive layer, a second conductive layer, and a third conductive layer that are sequentially stacked together; and
multiple transistors comprising six transistors, each of the six transistors comprising a first terminal, a second terminal, and a gate terminal,
wherein first, second, fourth, sixth transistors are in the first conductive layer and third and fifth transistors are in the third conductive layer, and wherein first terminals of the first, second, and third transistors are conductively coupled to a first conductive node in the second conductive layer, and first terminals of the fourth, fifth, and sixth transistors are conductively coupled to a second conductive node in the second conductive layer,
wherein a first conductive line in the metallic layer is configured to conductively couple the first conductive node to a gate terminal of the fourth transistor in the first conductive layer and a gate terminal of the fifth transistor in the third conductive layer, and wherein a second conducive line in the metallic layer is configured to conductively couple the second conductive node to a gate terminal of the second transistor in the first conductive layer and a gate terminal of the third transistor in the third conductive layer, and
wherein the multiple transistors further comprise: another second transistor in the third conductive layer, and wherein the first transistor and the third transistor are transistors of a first dopant type, and the second transistor and the another second transistor are transistors of a second dopant type that is different from the first dopant type.