Logic drive with brain-like elasticity and integrality based on standard commodity FPGA IC chips using non-volatile memory cells
A chip package comprises an interposer; an FPGA IC chip over the interposer, wherein the FPGA IC chip comprises a programmable logic block configured to perform a logic operation on its inputs, wherein the programmable logic block comprises a look-up table configured to be provided with multiple resulting values of the logic operation on multiple combinations of the inputs of the programmable logic block respectively, wherein the programmable logic block is configured to select, in accordance with one of the combinations of its inputs, one from the resulting values into its output, and multiple non-volatile memory cells configured to save the resulting values respectively; multiple first metal bumps between the interposer and the FPGA IC chip; and an underfill between the interposer and the FPGA IC chip, wherein the underfill encloses the first metal bumps.
1. A semiconductor integrated-circuit (IC) chip comprising:
a first non-volatile memory cell for storing a first programming code therein, wherein the first non-volatile memory cell has an output point for an output data thereof associated with the first programming code, wherein the first non-volatile memory cell comprises a first magnetoresistive-random-access-memory (MRAM) cell;
a first transistor configured to control coupling between a first node of the first non-volatile memory cell and a voltage (Vcc) of power supply;
a second transistor configured to control coupling between a second node of the first non-volatile memory cell and a voltage (Vss) of ground reference;
a switch having a first input point for a first input data associated with the output data of the first non-volatile memory cell; and
first and second programmable interconnects each coupling to the switch, wherein the switch is configured to control, in accordance with data associated with the first input data, coupling between the first and second programmable interconnects.
2. The semiconductor integrated-circuit (IC) chip of claim 1 further comprising a second non-volatile memory cell for storing a second programming code therein, wherein the second non-volatile memory cell comprises a second magnetoresistive-random-access-memory (MRAM) cell, and a third programmable interconnect coupling to the switch, wherein the switch has a second input point for a second input data associated with the second programming code, wherein the switch is configured to select, in accordance with a first data set thereof having data associated with the first and second input data, a third input data from a second data set thereof having data from the first and third programmable interconnects as an output data thereof, wherein the output data of the switch couples to the second programmable interconnect.
3. The semiconductor integrated-circuit (IC) chip of claim 1 , wherein the first transistor comprises a P-type metal-oxide-semiconductor (MOS) transistor configured to control the coupling between the first node of the first non-volatile memory cell and the voltage (Vcc) of power supply, and the second transistor comprises a N-type metal-oxide-semiconductor (MOS) transistor configured to control the coupling between the second node of the first non-volatile memory cell and the voltage (Vss) of ground reference.
4. The semiconductor integrated-circuit (IC) chip of claim 1 , wherein the first non-volatile memory cell further comprises a second magnetoresistive-random-access-memory (MRAM) cell between the second node of the first non-volatile memory cell and the output point of the first non-volatile memory cell, wherein the first magnetoresistive-random-access-memory (MRAM) cell is between the first node of the first non-volatile memory cell and the output point of the first non-volatile memory cell.
5. The semiconductor integrated-circuit (IC) chip of claim 1 , wherein the first magnetoresistive-random-access-memory (MRAM) cell comprises first and second magnetic layers and an oxide layer between the first and second magnetic layers.
6. The semiconductor integrated-circuit (IC) chip of claim 5 , wherein the oxide layer comprises magnesium oxide.
7. The semiconductor integrated-circuit (IC) chip of claim 5 , wherein the first magnetic layer comprises cobalt (Co), iron (Fe) and boron (B).
8. The semiconductor integrated-circuit (IC) chip of claim 5 , wherein the first magnetoresistive-random-access-memory (MRAM) cell further comprises an antiferromagnetic layer therein, wherein the first magnetic layer is between the oxide layer and the antiferromagnetic layer.
9. The semiconductor integrated-circuit (IC) chip of claim 1 is a field-programmable-gate-array (FPGA) integrated-circuit (IC) chip.
10. A semiconductor integrated-circuit (IC) chip comprising:
a first non-volatile memory cell for storing a first programming code therein, wherein the first non-volatile memory cell has an output point for an output data thereof associated with the first programming code;
a first transistor configured to control coupling between a first node of the first non-volatile memory cell and a voltage (Vcc) of power supply;
a second transistor configured to control coupling between a second node of the first non-volatile memory cell and a voltage (Vss) of ground reference;
a switch having a first input point for a first input data associated with the output data of the first non-volatile memory cell;
first and second programmable interconnects each coupling to the switch, wherein the switch is configured to control, in accordance with data associated with the first input data, coupling between the first and second programmable interconnects.
11. The semiconductor integrated-circuit (IC) chip of claim 10 further comprising a second non-volatile memory cell for storing a second programming code therein, and a third programmable interconnect coupling to the switch, wherein the switch has a second input point for a second input data associated with the second programming code, wherein the switch is configured to select, in accordance with a first data set thereof having data associated with the first and second input data, a third input data from a second data set thereof having data from the first and third programmable interconnects as an output data thereof, wherein the output data of the switch couples to the second programmable interconnect.
12. The semiconductor integrated-circuit (IC) chip of claim 10 , wherein the first transistor comprises a P-type metal-oxide-semiconductor (MOS) transistor configured to control the coupling between the first node of the first non-volatile memory cell and the voltage (Vcc) of power supply, and the second transistor comprises a N-type metal-oxide-semiconductor (MOS) transistor configured to control the coupling between the second node of the first non-volatile memory cell and the voltage (Vss) of ground reference.
13. The semiconductor integrated-circuit (IC) chip of claim 10 , wherein the first non-volatile memory cell comprises a programmable resistor between the first node of the first non-volatile memory cell and the output point of the first non-volatile memory cell.
14. The semiconductor integrated-circuit (IC) chip of claim 13 , wherein the programmable resistor comprises a magnetoresistive-random-access-memory (MRAM) cell between the first node of the first non-volatile memory cell and the output point of the first non-volatile memory cell.
15. The semiconductor integrated-circuit (IC) chip of claim 13 , wherein the programmable resistor comprises a resistive-random-access-memory (RRAM) cell between the first node of the first non-volatile memory cell and the output point of the first non-volatile memory cell.
16. The semiconductor integrated-circuit (IC) chip of claim 10 , wherein the first non-volatile memory cell comprises a programmable resistor between the second node of the first non-volatile memory cell and the output point of the first non-volatile memory cell.
17. The semiconductor integrated-circuit (IC) chip of claim 16 , wherein the programmable resistor comprises a magnetoresistive-random-access-memory (MRAM) cell between the second node of the first non-volatile memory cell and the output point of the first non-volatile memory cell.
18. The semiconductor integrated-circuit (IC) chip of claim 16 , wherein the programmable resistor comprises a resistive-random-access-memory (RRAM) cell between the second node of the first non-volatile memory cell and the output point of the first non-volatile memory cell.
19. The semiconductor integrated-circuit (IC) chip of claim 10 , wherein the first non-volatile memory cell comprises a first programmable resistor between the first node of the first non-volatile memory cell and the output point of the first non-volatile memory cell and a second programmable resistor between the second node of the first non-volatile memory cell and the output point of the first non-volatile memory cell.
20. The semiconductor integrated-circuit (IC) chip of claim 10 further comprising a semiconductor substrate, a plurality of transistors at a surface of the semiconductor substrate, a programmable-resistor layer over the surface of the semiconductor substrate and an interconnection scheme between the surface of the semiconductor substrate and the programmable-resistor layer, wherein interconnection scheme comprises an insulating dielectric layer and an interconnection metal layer in the insulating dielectric layer, wherein the programmable-resistor layer comprises a plurality of programmable resistors therein over the surface of the semiconductor substrate, wherein the first non-volatile memory cell comprises a programmable resistor provided by the plurality of programmable resistors in the programmable-resistor layer.