Variable bit line bias for nonvolatile memory
An apparatus is provided that includes a word line coupled to a word line driver circuit, bit lines, a plurality of non-volatile memory cells each coupled to the word line and a corresponding one of the bit lines, and a control circuit coupled to the word line and the bit lines. The control circuit is configured to program the memory cells by causing the word line driver to apply a program pulse to the word line, and biasing each bit line to a corresponding bit line voltage that has a value that varies based on a distance between the word line driver and the corresponding bit line.
1. An apparatus comprising:
a word line coupled to a word line driver circuit;
a plurality of bit lines;
a plurality of non-volatile memory cells each coupled to the word line and a corresponding one of the bit lines; and
a control circuit coupled to the word line and the bit lines, the control circuit configured to program the memory cells by:
causing the word line driver to apply a program pulse to the word line; and
biasing each bit line to a corresponding bit line voltage that decreases linearly with increasing distance between the word line driver and the corresponding bit line.
2. The apparatus of claim 1 , wherein the control circuit is further configured to program the memory cells by biasing each bit line to a corresponding unique bit line voltage that has a value that varies based on a distance between the word line driver and the corresponding bit line.
3. The apparatus of claim 1 , wherein the control circuit is further configured to program the memory cells by biasing each bit line to a corresponding unique bit line voltage that has a value that varies based on an amount of resistive-capacitive loading on the word line at a vicinity of the corresponding bit line as seen by the word line driver.
4. The apparatus of claim 1 , wherein the control circuit is further configured to program the memory cells by biasing each bit line to a corresponding bit line voltage that has a value that varies based on a distance between the word line driver and the corresponding bit line.
5. The apparatus of claim 1 , wherein the bit lines are not all biased to a same bit line voltage.
6. The apparatus of claim 1 , wherein no two bit lines are biased to a same bit line voltage.
7. The apparatus of claim 1 , wherein the control circuit is further configured to program the memory cells by causing the word line driver to apply a plurality of program pulses to the word line.
8. The apparatus of claim 1 , wherein the control circuit is further configured to program the memory cells without performing any verify operations.
9. The apparatus of claim 1 , wherein the control circuit is further configured to program the memory cells to natural threshold voltage distributions.
10. The apparatus of claim 1 , wherein the control circuit is further configured to program the memory cells between an erased state and a plurality of programmed states.
11. An apparatus comprising:
a word line coupled to a word line driver circuit;
a plurality of bit line groups each comprising one or more bit lines;
a plurality of non-volatile memory cells each coupled to the word line and a corresponding one of the bit lines; and
a control circuit coupled to the word line and the bit lines, the control circuit configured to program the memory cells by:
causing the word line driver to apply a program pulse to the word line; and
biasing bit lines in each bit line group to a corresponding group bit line voltage that has a value that decreases linearly with increasing distance between the word line driver and the corresponding bit line group.
12. The apparatus of claim 11 , wherein the control circuit is further configured to program the memory cells by biasing bit lines in each bit line group to a corresponding unique group bit line voltage that has a value that varies based on a distance between the word line driver and the corresponding bit line group.
13. The apparatus of claim 11 , wherein the control circuit is further configured to program the memory cells by biasing bit lines in each bit line group to a corresponding group bit line voltage that varies based on a distance between the word line driver and the corresponding bit line group.
14. The apparatus of claim 11 , wherein all group bit line voltages are not the same voltage.
15. The apparatus of claim 11 , wherein each bit line group comprises a same number of bit lines.
16. The apparatus of claim 11 , wherein the control circuit is further configured to program the memory cells without performing any verify operations.
17. The apparatus of claim 11 , wherein the control circuit is further configured to program the memory cells to natural threshold voltage distributions.
18. The apparatus of claim 11 , wherein the control circuit is further configured to program the memory cells between an erased state and a plurality of programmed states.
19. A method comprising:
programming a plurality of memory cells coupled to a word line that is coupled to a word line driver circuit, each memory cell coupled to a corresponding one of a plurality of bit lines, by:
causing the word line driver to apply a program pulse to the word line; and
biasing each bit line to a corresponding bit line voltage that:
has a value that varies based on an amount of resistive-capacitive loading on the word line at a vicinity of the corresponding bit line as seen by the word line driver; and
decreases linearly with increasing distance between the word line driver and the corresponding bit line.
20. The method of claim 19 , further comprising associating a first plurality of the bit lines with a first bit line group and associating a second plurality of the bit lines with a second bit line group, the bit lines in the first bit line group disposed closer to the word line driver than the bit lines of the second bit line group, wherein programming further comprises biasing bit lines in the first bit line group to a quick pass write voltage, and biasing bit lines in the second bit line group to ground.