Non-epitaxial electrical coupling between a front side trench connector and back side contacts of a transistor
Embodiments described herein may be related to creating a low resistance electrical path within a transistor between a front side trench connector and back side contacts and/or metal layers of the transistor. The low resistance electrical path does not go through a fin of the transistor that includes epitaxial material, but rather may go through a conductive path that does not include an epitaxial material. Embodiments may be compatible with a self-aligned back side contact architecture, which does not rely on deep via patterning. Other embodiments may be described and/or shown.
1 . A transistor comprising:
a gate;
a fin extending through the gate;
a conductive layer below the gate, the conductive layer having a first portion distinct from and laterally spaced apart from a second portion;
a trench connector directly electrically coupled with the fin; and
a connector directly electrically coupled with the trench connector, wherein the connector comprises metal, and wherein the connector has a bottom surface at a same level as a bottom surface of the fin, the bottom surface of the connector in direct contact with the first portion of the conductive layer, and the bottom surface of the fin in direct contact with the second portion of the conductive layer.
2 . The transistor of claim 1 , wherein the connector does not include an epitaxy.
3 . The transistor of claim 1 , wherein the conductive layer is at a back side of the transistor or the trench connector is at a front side of the transistor.
4 . The transistor of claim 1 , wherein the conductive layer is a backside connector.
5 . The transistor of claim 4 , further comprising a metal zero layer beneath the conductive layer, wherein the backside connector is electrically coupled with the metal zero layer.
6 . The transistor of claim 1 , wherein the trench connector and the connector include a metal.
7 . The transistor of claim 1 , wherein the fin is a plurality of fins, and wherein the trench connector is directly electrically coupled with the plurality of fins.
8 . The transistor of claim 1 , wherein the trench connector is a plurality of trench connectors, wherein the connector is a plurality of connectors; and
wherein the plurality of trench connectors are directly electrically coupled, respectively, with the plurality of connectors.
9 . The transistor of claim 1 , wherein the fin includes an epitaxy, and wherein the fin electrically couples the trench connector with the conductive layer.
10 . The transistor of claim 1 , wherein the fin is parallel to a direction of the gate.
11 . The transistor of claim 1 , wherein the gate is a plurality of gates.
12 . A package comprising:
an electrical component;
a transistor electrically coupled with the electrical component, the transistor comprising:
a front side and a backside opposite the front side;
a fin;
a first trench connector at the front side of the transistor;
a second trench connector and a third trench connector at the backside of the transistor, the third trench connector distinct from and laterally spaced apart from the second trench connector;
a connector directly electrically coupling the first trench connector with the second trench connector, wherein the connector comprises metal, and wherein the connector has a bottom surface at a same level as a bottom surface of the fin, the bottom surface of the connector in direct contact with the second trench connector, and the bottom surface of the fin in direct contact with the third trench connector.
13 . The package of claim 12 , further comprising:
a gate;
the fin extending through the gate; and
wherein the first trench connector is directly electrically coupled with the fin.
14 . The package of claim 13 , wherein the fin includes a plurality of fins; wherein the first trench connector is directly electrically coupled with the plurality of fins; and wherein the connector does not include an epitaxy.
15 . The package of claim 14 , wherein the plurality of fins are substantially parallel and overlap each other in a direction parallel to a direction of the gate.
16 . The package of claim 14 , wherein the plurality of fins are substantially parallel and overlap each other in a direction perpendicular to a direction of the gate.
17 . The package of claim 13 , wherein the gate is a plurality of gates, and wherein the fin extends through the plurality of gates.
18 . The package of claim 13 , wherein the fin includes epitaxy.
19 . The package of claim 12 , wherein the electrical component is a selected one or more of: a memory, an inductor, or a capacitor.
20 . The package of claim 12 , wherein the second trench connector at the backside of the transistor includes a metal zero layer.