IP Library › Granted Patent US 12,650,841
Granted Patent B2
US 12,650,841 · App. 17/712,075 · Granted Jun 9, 2026

Circuitry and methods for capability informed prefetches

Inventor: Scott D. Constable (Portland, OR)
Assignee: Intel Corporation
G06F9/30047G06F9/30145G06F9/383G06F12/0862G06F12/1458G06F2212/6026G06F2212/6028
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Quick Facts
Patent No.
US 12,650,841
App. No.
17/712,075
Granted
Jun 9, 2026
Kind
B2
Abstract

Systems, methods, and apparatuses for implementing capability informed prefetches are described. In certain examples, a hardware processor comprises an execution circuit to execute an instruction that generates a memory access request for an element in memory via a first capability; a capability management circuit to check the first capability for the memory access request, the first capability comprising an address field of the element in the memory, a validity field, and a bounds field that is to indicate a lower bound and an upper bound of a first object to which the first capability authorizes access; a cache; and a prefetch circuit to: prefetch an additional element from the memory to the cache, determine if the additional element is a second capability comprising an address field of a second element in the memory, a validity field, and a bounds field that is to indicate a lower bound and an upper bound of a second object to which the second capability authorizes access, and prefetch the second element from the memory to the cache based on the additional element being the second capability.

Claims (86)

1 . An apparatus comprising:

an execution circuit to execute an instruction that generates a memory access request for an element in memory via a first capability comprising an address field of the element in the memory, a validity field, and a bounds field that is to indicate a lower bound and an upper bound of a first object to which the first capability authorizes access;

a cache; and

a prefetch circuit to:

prefetch an additional element from the memory to the cache,

determine if the additional element is a second capability comprising an address field of a second element in the memory, a validity field, and a bounds field that is to indicate a lower bound and an upper bound of a second object to which the second capability authorizes access, and

prefetch the second element from the memory to the cache based on the additional element being the second capability,

wherein one of:

the prefetch circuit is to determine that the additional element is a candidate pointer in a chain of linked pointers, and the prefetch of the additional element from the memory to the cache is based on the additional element being the candidate pointer;

the prefetch circuit is to cause a prefetch of one or more further elements from the memory to the cache based on the second capability indicating the one or more further elements are within the second object, and the prefetch circuit is to:

determine if the one or more further elements is a respective capability comprising an address field of a respective element in the memory, a validity field, and a bounds field that is to indicate a lower bound and an upper bound of a respective object to which the respective capability authorizes access, and

prefetch the respective element from the memory to the cache for each of the one or more further elements that is the respective capability;

the prefetch circuit is to cause a prefetch of one or more further elements from the memory to the cache based on the second capability indicating the one or more further elements are within the second object, and the one or more further elements comprises a non-capability element and a capability element; or

the prefetch circuit is to cause a prefetch of one or more further elements from the memory to the cache based on the second capability indicating the one or more further elements are within the second object, and the prefetch circuit is to:

determine if the respective element is a further capability comprising an address field of another respective element in the memory, a validity field, and a bounds field that is to indicate a lower bound and an upper bound of a respective object to which the further capability authorizes access, and

prefetch the another respective element from the memory to the cache based on the respective element being the further capability.

2 . The apparatus of claim 1 , wherein the one is the prefetch circuit is to determine that the additional element is the candidate pointer in the chain of linked pointers, and the prefetch of the additional element from the memory to the cache is based on the additional element being the candidate pointer.

3 . The apparatus of claim 2 , wherein the prefetch circuit is to:

determine if the second element is a third capability comprising an address field of a third element in the memory, a validity field, and a bounds field that is to indicate a lower bound and an upper bound of a third object to which the third capability authorizes access; and

prefetch the third element from the memory to the cache based on the second element being the third capability.

4 . The apparatus of claim 1 , wherein the one is the prefetch circuit is to cause the prefetch of one or more further elements from the memory to the cache based on the second capability indicating the one or more further elements are within the second object, and the prefetch circuit is to:

determine if the one or more further elements is the respective capability comprising the address field of the respective element in the memory, the validity field, and the bounds field that is to indicate the lower bound and the upper bound of the respective object to which the respective capability authorizes access; and

prefetch the respective element from the memory to the cache for each of the one or more further elements that is the respective capability.

5 . The apparatus of claim 1 , wherein the one is the prefetch circuit is to cause the prefetch of one or more further elements from the memory to the cache based on the second capability indicating the one or more further elements are within the second object, and the one or more further elements comprises the non-capability element and the capability element.

6 . The apparatus of claim 5 , wherein the non-capability element is data to be operated on by the execution circuit.

7 . The apparatus of claim 1 , wherein the one is the prefetch circuit is to cause the prefetch of one or more further elements from the memory to the cache based on the second capability indicating the one or more further elements are within the second object, and the prefetch circuit is to:

determine if the respective element is the further capability comprising the address field of the another respective element in the memory, the validity field, and the bounds field that is to indicate the lower bound and the upper bound of the respective object to which the further capability authorizes access; and

prefetch the another respective element from the memory to the cache based on the respective element being the further capability.

8 . A method comprising:

executing, by an execution circuit of a processor, an instruction that generates a memory access request for an element in memory via a first capability comprising an address field of the element in the memory, a validity field, and a bounds field that is to indicate a lower bound and an upper bound of a first object to which the first capability authorizes access;

prefetching, by a prefetch circuit of the processor, an additional element from the memory to a cache of the processor;

determining, by the processor, if the additional element is a second capability comprising an address field of a second element in the memory, a validity field, and a bounds field that is to indicate a lower bound and an upper bound of a second object to which the second capability authorizes access;

prefetching, by the prefetch circuit, the second element from the memory to the cache based on the additional element being the second capability; and

further comprising one of:

determining, by the prefetch circuit, that the additional element is a candidate pointer in a chain of linked pointers, and the prefetching of the additional element from the memory to the cache is based on the additional element being the candidate pointer;

prefetching, by the prefetch circuit, one or more further elements from the memory to the cache based on the second capability indicating the one or more further elements are within the second object,

determining, by the processor, if the one or more further elements is a respective capability comprising an address field of a respective element in the memory, a validity field, and a bounds field that is to indicate a lower bound and an upper bound of a respective object to which the respective capability authorizes access, and

prefetching, by the prefetch circuit, the respective element from the memory to the cache for each of the one or more further elements that is the respective capability;

prefetching, by the prefetch circuit, one or more further elements from the memory to the cache based on the second capability indicating the one or more further elements are within the second object, wherein the one or more further elements comprises a non-capability element and a capability element; or

prefetching, by the prefetch circuit, one or more further elements from the memory to the cache based on the second capability indicating the one or more further elements are within the second object,

determining, by the processor, if the respective element is a further capability comprising an address field of another respective element in the memory, a validity field, and a bounds field that is to indicate a lower bound and an upper bound of a respective object to which the further capability authorizes access, and

prefetching, by the prefetch circuit, the another respective element from the memory to the cache based on the respective element being the further capability.

9 . The method of claim 8 , wherein the one is the determining, by the prefetch circuit, that the additional element is the candidate pointer in the chain of linked pointers, and the prefetching of the additional element from the memory to the cache is based on the additional element being the candidate pointer.

10 . The method of claim 9 , further comprising:

determining, by the processor, if the second element is a third capability comprising an address field of a third element in the memory, a validity field, and a bounds field that is to indicate a lower bound and an upper bound of a third object to which the third capability authorizes access; and

prefetching, by the prefetch circuit, the third element from the memory to the cache based on the second element being the third capability.

11 . The method of claim 8 , wherein the one is:

the prefetching, by the prefetch circuit, one or more further elements from the memory to the cache based on the second capability indicating the one or more further elements are within the second object;

the determining, by the processor, if the one or more further elements is the respective capability comprising the address field of the respective element in the memory, the validity field, and the bounds field that is to indicate the lower bound and the upper bound of the respective object to which the respective capability authorizes access; and

the prefetching, by the prefetch circuit, the respective element from the memory to the cache for each of the one or more further elements that is the respective capability.

12 . The method of claim 8 , wherein the one is the prefetching, by the prefetch circuit, one or more further elements from the memory to the cache based on the second capability indicating the one or more further elements are within the second object, and the one or more further elements comprises the non-capability element and the capability element.

13 . The method of claim 12 , wherein the non-capability element is data to be operated on by the execution circuit.

14 . The method of claim 8 , wherein the one is:

the prefetching, by the prefetch circuit, one or more further elements from the memory to the cache based on the second capability indicating the one or more further elements are within the second object;

the determining, by the processor, if the respective element is the further capability comprising the address field of the another respective element in the memory, the validity field, and the bounds field that is to indicate the lower bound and the upper bound of the respective object to which the further capability authorizes access; and

the prefetching, by the prefetch circuit, the another respective element from the memory to the cache based on the respective element being the further capability.

15 . A system comprising:

a memory;

a processor comprising:

an execution circuit to execute an instruction that generates a memory access request for an element in memory via a first capability comprising an address field of the element in the memory, a validity field, and a bounds field that is to indicate a lower bound and an upper bound of a first object to which the first capability authorizes access, and

a cache separate from the memory; and

a prefetch circuit to:

prefetch an additional element from the memory to the cache,

determine if the additional element is a second capability comprising an address field of a second element in the memory, a validity field, and a bounds field that is to indicate a lower bound and an upper bound of a second object to which the second capability authorizes access, and

prefetch the second element from the memory to the cache based on the additional element being the second capability

wherein one of:

the prefetch circuit is to determine that the additional element is a candidate pointer in a chain of linked pointers, and the prefetch of the additional element from the memory to the cache is based on the additional element being the candidate pointer;

the prefetch circuit is to cause a prefetch of one or more further elements from the memory to the cache based on the second capability indicating the one or more further elements are within the second object, and the prefetch circuit is to:

determine if the one or more further elements is a respective capability comprising an address field of a respective element in the memory, a validity field, and a bounds field that is to indicate a lower bound and an upper bound of a respective object to which the respective capability authorizes access, and

prefetch the respective element from the memory to the cache for each of the one or more further elements that is the respective capability;

the prefetch circuit is to cause a prefetch of one or more further elements from the memory to the cache based on the second capability indicating the one or more further elements are within the second object, and the one or more further elements comprises a non-capability element and a capability element; or

the prefetch circuit is to cause a prefetch of one or more further elements from the memory to the cache based on the second capability indicating the one or more further elements are within the second object, and the prefetch circuit is to:

determine if the respective element is a further capability comprising an address field of another respective element in the memory, a validity field, and a bounds field that is to indicate a lower bound and an upper bound of a respective object to which the further capability authorizes access, and

prefetch the another respective element from the memory to the cache based on the respective element being the further capability.

16 . The system of claim 15 , wherein the one is the prefetch circuit is to determine that the additional element is the candidate pointer in the chain of linked pointers, and the prefetch of the additional element from the memory to the cache is based on the additional element being the candidate pointer.

17 . The system of claim 16 , wherein the prefetch circuit is to:

determine if the second element is a third capability comprising an address field of a third element in the memory, a validity field, and a bounds field that is to indicate a lower bound and an upper bound of a third object to which the third capability authorizes access; and

prefetch the third element from the memory to the cache based on the second element being the third capability.

18 . The system of claim 15 , wherein the one is the prefetch circuit is to cause the prefetch of one or more further elements from the memory to the cache based on the second capability indicating the one or more further elements are within the second object, and the prefetch circuit is to:

determine if the one or more further elements is the respective capability comprising the address field of the respective element in the memory, the validity field, and the bounds field that is to indicate the lower bound and the upper bound of the respective object to which the respective capability authorizes access; and

prefetch the respective element from the memory to the cache for each of the one or more further elements that is the respective capability.

19 . The system of claim 15 , wherein the one is the prefetch circuit is to cause the prefetch of one or more further elements from the memory to the cache based on the second capability indicating the one or more further elements are within the second object, and the one or more further elements comprises the non-capability element and the capability element.

20 . The system of claim 19 , wherein the non-capability element is data to be operated on by the execution circuit.

21 . The system of claim 15 , wherein the one is the prefetch circuit is to cause the prefetch of one or more further elements from the memory to the cache based on the second capability indicating the one or more further elements are within the second object, and the prefetch circuit is to:

determine if the respective element is the further capability comprising the address field of the another respective element in the memory, the validity field, and the bounds field that is to indicate the lower bound and the upper bound of the respective object to which the further capability authorizes access; and

prefetch the another respective element from the memory to the cache based on the respective element being the further capability.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 11, 2022
From: CONSTABLE, SCOTT D.
To: INTEL CORPORATION
Reel/Frame 059560/0775 →
Continuity (1)
Related Publication 20230315452A1 · Oct 5, 2023
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