Granted Patent B2

US 12,417,099 · App. 17/712,073 · Granted Sep 16, 2025

Inventor: Scott D. Constable (Portland, OR)

Assignee: Intel Corporation

G06F9/30047G06F2212/1052G06F2212/6028

Abstract

Claims (54)

1. An apparatus comprising:

an execution circuit to execute an instruction that generates a memory access request for an element in memory via a first capability;

a capability management circuit to check the first capability for the memory access request, the first capability comprising an address field of the element in the memory, a validity field, and a bounds field that is to indicate a lower bound and an upper bound of a first object to which the first capability authorizes access;

a cache; and

a prefetch circuit to:

prefetch an additional element of the first object from the memory based on the first capability checked by the capability management circuit,

determine if the additional element is a second capability comprising an address field of a second element in the memory, a validity field, and a bounds field that is to indicate a lower bound and an upper bound of a second object to which the second capability authorizes access, and

prefetch the second element from the memory to the cache based on the additional element being the second capability.

2. The apparatus of claim 1 , wherein the prefetch circuit is to prefetch the additional element of the first object from the memory to the cache based on the first capability.

3. The apparatus of claim 1 , wherein the prefetch circuit is to cause a prefetch of one or more further elements of the second object from the memory to the cache based on the one or more further elements being within the lower bound and the upper bound indicated by the second capability.

4. The apparatus of claim 3 , wherein the one or more further elements of the second object are a plurality of further elements of the second object within the lower bound and the upper bound indicated by the second capability.

5. The apparatus of claim 3 , wherein the prefetch circuit comprises a plurality of prefetch circuits, and the plurality of prefetch circuits are to prefetch the second element from the memory to the cache in parallel with the prefetch of the one or more further elements of the second object from the memory to the cache.

6. The apparatus of claim 1 , wherein the prefetch circuit is to:

prefetch a second additional element of the first object from the memory based on the first capability,

determine if the second additional element is a third capability comprising an address field of a third element in the memory, a validity field, and a bounds field that is to indicate a lower bound and an upper bound of a third object to which the third capability authorizes access, and

prefetch the third element from the memory to the cache based on the second additional element being the third capability.

7. The apparatus of claim 6 , wherein the prefetch circuit is to cause a prefetch of one or more further elements of the third object from the memory to the cache based on the one or more further elements being within the lower bound and the upper bound indicated by the third capability.

8. The apparatus of claim 1 , wherein the prefetch circuit is to prefetch the additional element of the first object from the memory based on the additional element being within the lower bound and the upper bound of the first object indicated by the first capability.

9. A method comprising:

executing, by an execution circuit of a processor, an instruction that generates a memory access request for an element in memory via a first capability;

checking, by a capability management circuit of the processor, the first capability for the memory access request, the first capability comprising an address field of the element in the memory, a validity field, and a bounds field that is to indicate a lower bound and an upper bound of a first object to which the first capability authorizes access;

prefetching, by a prefetch circuit of the processor, an additional element of the first object from the memory based on the first capability checked by the capability management circuit;

determining, by the processor, if the additional element is a second capability comprising an address field of a second element in the memory, a validity field, and a bounds field that is to indicate a lower bound and an upper bound of a second object to which the second capability authorizes access; and

prefetching, by the prefetch circuit, the second element from the memory to a cache of the processor based on the additional element being the second capability.

10. The method of claim 9 , wherein the prefetching of the additional element comprises prefetching the additional element of the first object from the memory to the cache based on the first capability.

11. The method of claim 9 , further comprising prefetching, by the prefetch circuit, one or more further elements of the second object from the memory to the cache based on the one or more further elements being within the lower bound and the upper bound indicated by the second capability.

12. The method of claim 11 , wherein the one or more further elements of the second object are a plurality of further elements of the second object within the lower bound and the upper bound indicated by the second capability.

13. The method of claim 11 , wherein the prefetch circuit comprises a plurality of prefetch circuits, and the plurality of prefetch circuits perform the prefetching of the second element from the memory to the cache in parallel with the prefetching of the one or more further elements of the second object from the memory to the cache.

14. The method of claim 9 , further comprising:

prefetching, by the prefetch circuit, a second additional element of the first object from the memory based on the first capability;

determining, by the processor, if the second additional element is a third capability comprising an address field of a third element in the memory, a validity field, and a bounds field that is to indicate a lower bound and an upper bound of a third object to which the third capability authorizes access; and

prefetching, by the prefetch circuit, the third element from the memory to the cache based on the second additional element being the third capability.

15. The method of claim 14 , further comprising prefetching, by the prefetch circuit, one or more further elements of the third object from the memory to the cache based on the one or more further elements being within the lower bound and the upper bound indicated by the third capability.

16. The method of claim 9 , wherein the prefetching of the additional element of the first object from the memory is based on the additional element being within the lower bound and the upper bound of the first object indicated by the first capability.

17. A system comprising:

a memory;

a processor comprising:

an execution circuit to execute an instruction that generates a memory access request for an element in the memory via a first capability, and

a cache separate from the memory;

a capability management circuit to check the first capability for the memory access request, the first capability comprising an address field of the element in the memory, a validity field, and a bounds field that is to indicate a lower bound and an upper bound of a first object to which the first capability authorizes access; and

a prefetch circuit to:

prefetch an additional element of the first object from the memory based on the first capability checked by the capability management circuit,

determine if the additional element is a second capability comprising an address field of a second element in the memory, a validity field, and a bounds field that is to indicate a lower bound and an upper bound of a second object to which the second capability authorizes access, and

prefetch the second element from the memory to the cache based on the additional element being the second capability.

18. The system of claim 17 , wherein the prefetch circuit is to prefetch the additional element of the first object from the memory to the cache based on the first capability.

19. The system of claim 17 , wherein the prefetch circuit is to cause a prefetch of one or more further elements of the second object from the memory to the cache based on the one or more further elements being within the lower bound and the upper bound indicated by the second capability.

20. The system of claim 19 , wherein the one or more further elements of the second object are a plurality of further elements of the second object within the lower bound and the upper bound indicated by the second capability.

21. The system of claim 19 , wherein the prefetch circuit comprises a plurality of prefetch circuits, and the plurality of prefetch circuits are to prefetch the second element from the memory to the cache in parallel with the prefetch of the one or more further elements of the second object from the memory to the cache.

22. The system of claim 17 , wherein the prefetch circuit is to:

prefetch a second additional element of the first object from the memory based on the first capability,

determine if the second additional element is a third capability comprising an address field of a third element in the memory, a validity field, and a bounds field that is to indicate a lower bound and an upper bound of a third object to which the third capability authorizes access, and

prefetch the third element from the memory to the cache based on the second additional element being the third capability.

23. The system of claim 22 , wherein the prefetch circuit is to cause a prefetch of one or more further elements of the third object from the memory to the cache based on the one or more further elements being within the lower bound and the upper bound indicated by the third capability.

24. The system of claim 17 , wherein the prefetch circuit is to prefetch the additional element of the first object from the memory based on the additional element being within the lower bound and the upper bound of the first object indicated by the first capability.

Assignments (1)

Continuity (1)

References Cited (142)