Circuitry and methods for implementing capability-directed prefetching
Systems, methods, and apparatuses for implementing capability-directed array prefetching are described. In certain examples, a hardware processor comprises an execution circuit to execute an instruction that generates a memory access request for an element in memory; a capability management circuit to check a capability for the memory access request, the capability comprising an address field of the element in the memory, a validity field, and a bounds field that is to indicate a lower bound and an upper bound of an object to which the capability authorizes access; a cache; and a prefetch circuit to prefetch an additional element of the object from the memory to the cache based on the capability checked by the capability management circuit.
1 . An apparatus comprising:
an execution circuit to execute an instruction that generates a memory access request for an element in memory via a capability;
a capability management circuit to check the capability for the memory access request, the capability comprising an address field of the element in the memory, a validity field, and a bounds field that is to indicate a lower bound and an upper bound of an object to which the capability authorizes access;
a cache; and
a prefetch circuit to prefetch an additional element of the object from the memory to the cache based on the capability checked by the capability management circuit.
2 . The apparatus of claim 1 , wherein the prefetch circuit comprises a data structure to store a mapping of capabilities of the memory to their most recent access.
3 . The apparatus of claim 2 , wherein the prefetch circuit is to cause the prefetch of the additional element from the memory based on:
the mapping in the data structure for the capability indicating the additional element is not a most recent accessed element for the capability; and
the additional element being within the lower bound and the upper bound indicated by the capability for the object.
4 . The apparatus of claim 2 , wherein the prefetch circuit is to, in response to the prefetch of the additional element from the memory, update the mapping in the data structure for the capability to indicate the additional element is a most recent accessed element for the capability.
5 . The apparatus of claim 2 , wherein the prefetch circuit is to cause a prefetch of one or more further elements from the memory based on:
the mapping for the capability indicating the one or more further elements is not a most recent accessed element for the capability; and
the one or more further elements being within the lower bound and the upper bound indicated by the capability for the object.
6 . The apparatus of claim 5 , wherein the data structure is to store a mapping of capabilities in the memory to their most recent prefetched element, and stop the prefetch of the one or more further elements based on the mapping indicating a most recent prefetched element is a last element within the upper bound indicated by the capability for the object.
7 . The apparatus of claim 1 , wherein the prefetch circuit is to only prefetch the additional element of the object from the memory to the cache when the element in the memory is a second or greater access of the object by the execution circuit.
8 . The apparatus of claim 1 , wherein the prefetch circuit is to prefetch the additional element of the object from the memory to the cache based on the additional element being within the lower bound and the upper bound of the object indicated by the capability for the object.
9 . A method comprising:
executing, by an execution circuit of a processor, an instruction that generates a memory access request for an element in memory via a capability;
checking, by a capability management circuit of the processor, the capability for the memory access request, the capability comprising an address field of the element in the memory, a validity field, and a bounds field that is to indicate a lower bound and an upper bound of an object to which the capability authorizes access; and
prefetching, by a prefetch circuit of the processor, an additional element of the object from the memory to a cache of the processor based on the capability checked by the capability management circuit.
10 . The method of claim 9 , further comprising storing, by the prefetch circuit in a data structure, a mapping of capabilities of the memory to their most recent access.
11 . The method of claim 10 , wherein the prefetching of the additional element from the memory is based on:
the mapping in the data structure for the capability indicating the additional element is not a most recent accessed element for the capability; and
the additional element being within the lower bound and the upper bound indicated by the capability for the object.
12 . The method of claim 10 , further comprising, in response to the prefetch of the additional element from the memory, updating, by the prefetch circuit, the mapping in the data structure for the capability to indicate the additional element is a most recent accessed element for the capability.
13 . The method of claim 10 , further comprising prefetching one or more further elements from the memory based on:
the mapping for the capability indicating the one or more further elements is not a most recent accessed element for the capability; and
the one or more further elements being within the lower bound and the upper bound indicated by the capability for the object.
14 . The method of claim 13 , further comprising:
storing, by the prefetch circuit in the data structure, a mapping of capabilities in the memory to their most recent prefetched element; and
stopping the prefetch of the one or more further elements based on the mapping indicating a most recent prefetched element is a last element within the upper bound indicated by the capability for the object.
15 . The method of claim 9 , wherein the prefetching of the additional element of the object from the memory to the cache is only when the element in the memory is a second or greater access of the object by the execution circuit.
16 . The method of claim 9 , wherein the prefetching of the additional element of the object from the memory to the cache is based on the additional element being within the lower bound and the upper bound of the object indicated by the capability for the object.
17 . A system comprising:
a memory;
a processor comprising:
an execution circuit to execute an instruction that generates a memory access request for an element in the memory via a capability, and
a cache separate from the memory;
a capability management circuit to check the capability for the memory access request, the capability comprising an address field of the element in the memory, a validity field, and a bounds field that is to indicate a lower bound and an upper bound of an object to which the capability authorizes access; and
a prefetch circuit to prefetch an additional element of the object from the memory to the cache based on the capability checked by the capability management circuit.
18 . The system of claim 17 , wherein the prefetch circuit comprises a data structure to store a mapping of capabilities of the memory to their most recent access.
19 . The system of claim 18 , wherein the prefetch circuit is to cause the prefetch of the additional element from the memory based on:
the mapping in the data structure for the capability indicating the additional element is not a most recent accessed element for the capability; and
the additional element being within the lower bound and the upper bound indicated by the capability for the object.
20 . The system of claim 18 , wherein the prefetch circuit is to, in response to the prefetch of the additional element from the memory, update the mapping in the data structure for the capability to indicate the additional element is a most recent accessed element for the capability.
21 . The system of claim 18 , wherein the prefetch circuit is to cause a prefetch of one or more further elements from the memory based on:
the mapping for the capability indicating the one or more further elements is not a most recent accessed element for the capability; and
the one or more further elements being within the lower bound and the upper bound indicated by the capability for the object.
22 . The system of claim 21 , wherein the data structure is to store a mapping of capabilities in the memory to their most recent prefetched element, and stop the prefetch of the one or more further elements based on the mapping indicating a most recent prefetched element is a last element within the upper bound indicated by the capability for the object.
23 . The system of claim 17 , wherein the prefetch circuit is to only prefetch the additional element of the object from the memory to the cache when the element in the memory is a second or greater access of the object by the execution circuit.
24 . The system of claim 17 , wherein the prefetch circuit is to prefetch the additional element of the object from the memory to the cache based on the additional element being within the lower bound and the upper bound of the object indicated by the capability for the object.