3D memory devices and structures with multiple memory levels
A semiconductor device, the device including: a first level overlaid by a first memory control level; a first memory level disposed on top of said first control level, where said first memory level includes a first thinned single crystal substrate; a second memory level, said second memory level disposed on top of said first memory level, where said second memory level includes a second thinned single crystal substrate, where said memory control level is bonded to said first memory level, and where said bonded includes oxide to oxide and conductor to conductor bonding.
1. A semiconductor device, the device comprising:
a first level comprising control circuits;
a first memory level disposed on top of said first level,
wherein said first memory level comprises a first substrate; and
a second memory level,
wherein said second memory level is disposed on top of said first memory level,
wherein said control circuits control said first memory level,
wherein said second memory level comprises a second substrate,
wherein said first level is bonded to said first memory level, and
wherein said bonded comprises oxide to oxide bonding.
2. The device according to claim 1 ,
wherein a thickness of said first substrate is less than 30 microns and greater than 0.1 microns.
3. The device according to claim 1 , further comprising:
a logic level disposed either above or below said first memory level; and
a thermal isolation layer disposed between said logic level and said first memory level,
wherein said thermal isolation layer is designed so during operation of said device a first temperature of memory cells of said first memory level is at least 20° C. lower than a second temperature of said logic level.
4. The device according to claim 1 ,
wherein said second substrate comprises a second thinned single crystal substrate.
5. The device according to claim 1 ,
wherein said second memory level is second bonded to said first memory level, and
wherein said second bonded comprises oxide to oxide bonding.
6. The device according to claim 1 ,
wherein a portion of said first memory level is used as a first alternative for a portion of said second memory level, or a portion of said second memory level is used as a second alternative for a portion of said first memory level.
7. The device according to claim 1 ,
wherein said device is diced from a wafer structure resulting in a die with a planar size greater than 40 mm×40 mm.
8. A semiconductor device, the device comprising:
a memory control level comprising control circuits;
a first memory level disposed on top of said memory control level,
wherein said first memory level comprises a first substrate;
a second memory level disposed on top of said first memory level,
wherein said second memory level comprises a second substrate,
wherein said first memory level is first bonded to said memory control level; and
a third memory level disposed on top of said second memory level,
wherein said third memory level comprises a third substrate,
wherein said third memory level is second bonded to said second memory level,
wherein said control circuits control said first memory level, and
wherein said first bonded and said second bonded comprise oxide to oxide bonding.
9. The device according to claim 8 ,
wherein a thickness of said first substrate is less than 30 microns and greater than 0.1 microns.
10. The device according to claim 8 , further comprising:
a logic level disposed either above or below said first memory level; and
a thermal isolation layer disposed between said logic level and said first memory level,
wherein said thermal isolation layer is designed so during said device operation a first temperature of memory cells of said first memory level is at least 20° C. lower than a second temperature of said logic level.
11. The device according to claim 8 ,
wherein said second substrate comprises a second thinned single crystal substrate.
12. The device according to claim 8 ,
wherein said second memory level is third bonded to said first memory level, and
wherein said third bonded comprises oxide to oxide bonding.
13. The device according to claim 8 ,
wherein a portion of said first memory level is used as a first alternative for a portion of said second memory level, or a portion of said second memory level is used as a second alternative for a portion of said first memory level.
14. The device according to claim 8 ,
wherein said device has been diced from a wafer structure resulting in a planar size greater than 40 mm×40 mm.
15. A semiconductor device, the device comprising:
a memory control level comprising control circuits;
a first memory level disposed on top of said memory control level,
wherein said first memory level comprises a first substrate;
a second memory level disposed on top of said first memory level,
wherein said second memory level comprises a second substrate; and
a third memory level disposed on top of said second memory level,
wherein said third memory level comprises a third substrate,
wherein said second memory level is first bonded to said first memory level,
wherein said first bonded comprises oxide to oxide bonding,
wherein said memory control level comprises a fourth substrate,
wherein said control circuits control said first memory level, and
wherein a plurality of vias (“TSV”) are disposed through said fourth substrate.
16. The device according to claim 15 ,
wherein a thickness of said first substrate is less than 25 microns and greater than 0.1 microns.
17. The device according to claim 15 , further comprising:
a logic level disposed either above or below said first memory level; and
a thermal isolation layer disposed between said logic level and said first memory level,
wherein said thermal isolation layer is designed so during said device operation a first temperature of memory cells of said first memory level is at least 20° C. lower than a second temperature of said logic level.
18. The device according to claim 15 ,
wherein said first bonded additionally comprises conductor to conductor bonding.
19. The device according to claim 15 ,
wherein a portion of said first memory level is used as a first alternative for a portion of said second memory level, or a portion of said second memory level is used as a second alternative for a portion of said first memory level.
20. The device according to claim 15 ,
wherein said device has been diced from a wafer structure resulting in a planar size greater than 40 mm×40 mm.