Pixel for micro-display having vertically stacked sub-pixels
A unit pixel of a microdisplay is disclosed. In the unit pixel, sub-pixels that form blue light, green light, and red light are vertically stacked on a growth substrate. Accordingly, the unit pixel area may be reduced, and pixel transfer processing is facilitated.
1. A unit pixel of a microdisplay, comprising:
a first sub-pixel formed on a growth substrate;
a second sub-pixel formed on the first sub-pixel;
a common electrode layer formed between the first sub-pixel and the second sub-pixel;
a third sub-pixel formed on the second sub-pixel; and
a contact layer formed between the growth substrate and the first sub-pixel, and independently connected to each of the first sub-pixel, the second sub-pixel, and the third sub-pixel;
wherein the contact layer includes:
a first n-type contact layer formed on the growth substrate and connected to the third sub-pixel;
a second n-type contact layer formed on the first n-type contact layer and connected to the second sub-pixel;
a third n-type contact layer formed on the second n-type contact layer and connected to the first sub-pixel;
a first current blocking layer formed between the first n-type contact layer and the second n-type contact layer; and
a second current blocking layer formed between the second n-type contact layer and the third n-type contact layer.
2. The unit pixel of claim 1 , wherein the first current blocking layer and the second current blocking layer are each a p-type semiconductor or an insulating material.
3. The unit pixel of claim 1 , further comprising:
a first tunnel junction layer formed between the common electrode layer and the first sub-pixel; and
a second tunnel junction layer formed between the common electrode layer and the second sub-pixel.
4. The unit pixel of claim 1 , wherein
the first sub-pixel includes a first n-type semiconductor layer, a first active layer, and a first p-type semiconductor layer which are sequentially stacked,
the second sub-pixel includes a second p-type semiconductor layer, a second active layer, and a second n-type semiconductor layer which are sequentially stacked, and
the third sub-pixel includes a third n-type semiconductor layer, a third active layer, and a third p-type semiconductor layer which are sequentially stacked.
5. The unit pixel of claim 4 , further comprising a third current blocking layer formed between the second sub-pixel and the third sub-pixel.
6. The unit pixel of claim 5 , wherein the third current blocking layer is a p-type semiconductor or an insulating material.
7. The unit pixel of claim 4 , further comprising:
a first interconnect layer configured to electrically connect the second n-type semiconductor layer and the second n-type contact layer;
a second interconnect layer configured to electrically connect the third n-type semiconductor layer and the first n-type contact layer; and
a common anode formed on an exposed surface of the common electrode layer and covering the third p-type semiconductor layer.
8. The unit pixel of claim 7 , wherein
the first interconnect layer is formed on an exposed portion of each of the second n-type semiconductor layer and the second n-type contact layer, and
the second interconnect layer is formed on an exposed portion of each of the third n-type semiconductor layer and the first n-type contact layer to extend from the third n-type semiconductor layer to the first n-type contact layer.
9. The unit pixel of claim 1 , wherein
the first sub-pixel includes a first n-type semiconductor layer, a first active layer, and a first p-type semiconductor layer which are sequentially stacked,
the second sub-pixel includes a second p-type semiconductor layer, a second active layer, and a second n-type semiconductor layer which are sequentially stacked, and
the third sub-pixel includes a third p-type semiconductor layer, a third active layer, and a third n-type semiconductor layer which are sequentially stacked.
10. The unit pixel of claim 9 , further comprising
a bonding layer formed between the second sub-pixel and the third sub-pixel.
11. The unit pixel of claim 9 , further comprising:
a first interconnect layer configured to electrically connect the second n-type semiconductor layer and the second n-type contact layer;
a second interconnect layer configured to electrically connect the third n-type semiconductor layer and the first n-type contact layer; and
a common anode formed on the common electrode layer and the third p-type semiconductor layer and covering the third n-type semiconductor layer,
wherein the common anode is formed to be insulated from the third n-type semiconductor layer.
12. The unit pixel of claim 11 , wherein
the first interconnect layer is formed on an exposed portion of each of the second n-type semiconductor layer and the second n-type contact layer, and
the second interconnect layer is formed on an exposed portion of each of the third n-type semiconductor layer and the first n-type contact layer to extend from the third n-type semiconductor layer to the first n-type contact layer.
13. The unit pixel of claim 9 , wherein the third active layer includes AlInGaP.