Methods of forming dislocation enhanced strain in NMOS and PMOS structures
Methods of forming a strained channel device utilizing dislocations disposed in source/drain structures are described. Those methods and structures may include forming a thin silicon germanium material in a source/drain opening of a device comprising silicon, wherein multiple dislocations are formed in the silicon germanium material. A source/drain material may be formed on the thin silicon germanium material, wherein the dislocations induce a tensile strain in a channel region of the device.
1. A method for fabricating a strained-channel FET transistor comprising:
presenting a single-crystal semiconductor substrate of a material having a first lattice constant;
forming a fin of single-crystal semiconductor projecting from the single-crystal semiconductor substrate, the fin extending from a source region, through a channel region, to a drain region;
forming an isolation dielectric about the fin of single-crystal semiconductor;
forming a gate dielectric on the channel region of the fin of single-crystal semiconductor;
depositing a gate electrode upon the gate dielectric;
etching a first opening in the source region of the fin of single-crystal semiconductor;
etching a second opening in the drain region of the fin of single-crystal semiconductor;
epitaxially growing a source nucleation layer having a second lattice constant different from the first lattice constant within the first opening in the source region of the fin of single-crystal semiconductor;
epitaxially growing a drain nucleation layer having the second lattice constant within the second opening in the drain region the single-crystal semiconductor semiconductor; wherein the second lattice constant is between 5.43 Å and 5.66 Å; wherein each of source and drain materials comprise arsenic and/or phosphorus; wherein the arsenic and/or phosphorus has a concentration between 10 16 cm −3 and 10 21 cm −3 .
2. The method of claim 1 , further comprising:
causing crystalline dislocations to form within the source and drain regions.
3. The method of claim 2 , further comprising:
epitaxially growing source material upon the source nucleation layer, the source material propagating dislocations caused to form within the source region; and
epitaxially growing drain material upon the drain nucleation layer, the drain material propagating the dislocations caused to form within the drain region.
4. The method of claim 1 , wherein the first and second openings in the source and drain regions, respectively, are formed using a wet etchant.
5. The method of claim 1 , wherein the first and second openings in the source and drain regions, respectively, are formed using a dry etch process.
6. The method of claim 1 , further comprising:
forming a dielectric spacer on sides of the gate electrode.
7. The method of claim 1 , wherein the single-crystal semiconductor substrate comprises silicon.
8. The method of claim 1 , wherein each of the source and drain materials comprises silicon-germanium.
9. The method of claim 8 , wherein the silicon-germanium of the source and drain materials has a germanium concentration between 10% and 80%.
10. The method of claim 8 , wherein the silicon-germanium of the source and drain materials is undoped.
11. The method of claim 1 , further comprising:
forming a nanowire extending from the source region to the drain region.
12. The method of claim 11 , wherein the nanowire comprises silicon.
13. The method of claim 12 , wherein the gate dielectric surrounds the nanowire.